Digital Front-End Lead – RTL & Design Verification

NYXSES India Private Limited; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

A leading semiconductor company in Bengaluru is seeking a highly experienced Digital Front-End Lead. The candidate will drive SoC/MCU architecture, ensure RTL quality, and mentor a skilled team. Responsibilities include defining verification strategies, developing verification environments, and supporting silicon bring-up. Ideal candidates have 8–15 years in ASIC/SoC Digital Front-End with strong expertise in RTL Design and Chip-Level Verification, preferably with ARM-based MCU products.

Qualifications

• 8–15 years in ASIC/SoC Digital Front-End.
• Strong expertise in RTL Design and Chip-Level Verification.
• Experience with MCU/ARM-based SoCs.

Responsibilities

• Define and own chip-level verification strategy and plan.
• Extract use cases and derive verification scenarios.
• Develop dynamic & static verification environments.
• Drive coverage closure and Gate-Level Simulation (GLS).
• Ensure robust verification sign-off.

Skills

RTL Design

Chip-Level Verification

SoC/MCU architecture

Dynamic verification environments

Static verification environments

Job description

We are looking for a highly experienced Digital Front-End Lead with strong expertise in RTL Design and Chip-Level Verification. The ideal candidate will be a hands‑on technical leader capable of driving SoC/MCU architecture, RTL quality, and end‑to‑end verification closure while mentoring a high‑performing team.

Experience with ARM-based MCU products is highly preferred.

Key Responsibilities

• Define and own chip‑level verification strategy and plan
• Extract use cases and derive verification scenarios
• Develop dynamic & static verification environments
• Drive coverage closure and Gate‑Level Simulation (GLS) with back‑annotated delays
• Ensure robust verification sign‑off

2. RTL Design & Quality

• Define RTL coding standards and quality metrics
• Perform RTL reviews and lint/quality checks using EDA tools

3. Synthesis & Timing

• Create and validate SDC constraints
• Run synthesis trials and review STA reports
• Coordinate with backend for timing closure
• Lead and mentor DFE/Verification engineers
• Plan milestones and track execution
• Work closely with Backend, Analog, and Test teams
• Support silicon bring‑up and production validation

Required Experience

• 8–15 years in ASIC / SoC Digital Front‑End
• Strong expertise in RTL Design and Chip‑Level Verification
• Experience with MCU/ARM‑based SoCs