Design Engineer

Tekskills Inc.; Hyderabad; On-site; INR 4,000,000 - 7,500,000; Full time

Job summary

Tekskills Inc. is hiring a Digital Front-End Lead in Hyderabad, India. The role requires 8-15 years of experience and focuses on driving chip-level architecture, RTL design and verification while mentoring a high-performing team.

The ideal candidate will lead verification strategies, contribute to architectural decisions, and coordinate with backend/analog teams. MCU/ARM core experience is a plus; only non-FPGA products are targeted.

Qualifications

• 8-15 years of experience in digital frontend/SoC environments.
• Leadership with mentoring of high-performing teams.
• Strong background in chip-level architecture, RTL design and verification.
• Experience with MCU products and ARM cores is a plus.

Responsibilities

• Chip-Level Use Case Understanding.
• Verification Plan Formulation, Management, and Review.
• Extraction of verification items and stimulus specs.
• Building Dynamic & Static Verification Environments.
• Gate-Level Simulation with Back-Annotated Delays.
• Leadership in DFE team management and documentation.
• RTL Design & Quality Verification and architecture design.
• Constraint Creation and Synthesis (SDC/STA).
• Power System Design and Mass Production support.
• Testing, On-Board Evaluation, and ATE pattern generation.

Skills

Leadership

Mentoring

Cross-functional collaboration

Frontend architecture

Tools

Verilog HDL

SystemVerilog

EDA Tools

Job description

We are hiring for Digital Front End Lead

Job Title: Digital Front-End Lead Work

Experience: 8-15 years

• We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.


• This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.* Target products are not FPGA-based.**Experience with MCU products featuring ARM cores is preferred. *

Chip Level Verification

• Chip-Level Use Case Understanding


• Verification Plan Formulation, Management, and Review


• Extraction of verification items and formulation of verification program stimulus specifications


• Building Dynamic & Static Verification Environments


• Gate-Level Simulation with Back-Annotated Delays

Management

• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team

DFE Team Management

• Documentation


• Continuous Improvement Suggestions


• Functional Safety Standards

RTL Design & Quality Verification

• RTL Quality Control


• RTL Coding Skills (Verilog HDL/System Verilog)


• RTL Quality Check Execution; EDA Tools for RTL Quality Checks

Architecture Design

• Chip-Level System Architecture Design


• Block-level microarchitecture design

Constraint Creation and Synthesis (SDC/STA)

• Timing and synthesis constraints


• Synthesis trial and STA report confirmation

Chip Level Assembly

• Chip-Level Assembly Using EDA Tools

Power System Design

• Multi-Power Domain Design


• Power System Model Design

Testing, On-Board Evaluation, and Mass Production Support

• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)


• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)

Power Estimate

• Power Analysis Using EDA Tools and Design Feedback


• Power Estimation During Feasibility Stage