Digital Front-End Lead

Tekskills Inc.; Chennai; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Tekskills Inc. in Chennai seeks a Digital Front-End Lead to drive chip-level architecture, RTL design, and verification while mentoring a high-performing team.

You will lead verification strategies, coordinate with backend and analog teams, and contribute to SoC design decisions to ensure robust products. Advanced RTL coding (Verilog/SystemVerilog) and experience with EDA tools are preferred, with a focus on continuous improvement and project leadership.

Qualifications

• High-level capability in chip verification and design required.
• Experience leading a verification team and coordinating with back-end and analog groups.
• Strong RTL coding skills (Verilog/SystemVerilog) and use of EDA tools.
• Ability to drive architecture design and timing constraints for a multi-block SoC.
• Experience with synthesis constraints and power-aware design considerations.

Responsibilities

• Lead chip-level architecture, RTL design, and verification while mentoring a team.
• Define and manage verification plans, stimuli, and environments.
• Collaborate with backend/analog teams and drive continuous process improvements.
• Contribute to SoC-level architectural decisions and project management.

Skills

Chip Level Verification

Management

RTL Design & Verification

Architecture Design

Constraint Creation

Chip Level Assembly

Power System Design

Testing & Evaluation

Power Estimation

ARM MCU Experience

Job description

Role & responsibilities

Job Summary

We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.

This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.

Key Skills - Priority Level (1-5)

• Chip Level Verification 5
• Chip-Level Use Case Understanding
• Verification Plan Formulation, Management, and Review
• Extraction of verification items and formulation of verification program stimulus specifications
• Building Dynamic & Static Verification Environments
• Gate-Level Simulation with Back-Annotated Delays
• Management -5
• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team
• DFE Team Management
• Documentation
• Continuous Improvement Suggestions
• Functional Safety Standards
• RTL Design & Quality Verification - 4
• RTL Quality Control
• RTL Coding Skills (Verilog HDL/System Verilog)
• RTL Quality Check Execution; EDA Tools for RTL Quality Checks
• Architecture Design 3
• Chip-Level System Architecture Design
• Block-level microarchitecture design
• Constraint Creation and Synthesis (SDC/STA) - 3
• Timing and synthesis constraints
• Synthesis trial and STA report confirmation
• Chip Level Assembly 3
• Chip-Level Assembly Using EDA Tools
• Power System Design- 3
• Multi-Power Domain Design
• Power System Model Design
• Testing, On-Board Evaluation, and Mass Production Support- 3
• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)
• Power Estimate- 2
• Power Analysis Using EDA Tools and Design Feedback
• Power Estimation During Feasibility Stage

Preferred candidate profile

xperience with MCU products featuring ARM cores is preferred. *

* Target products are not FPGA-based.*