Digital Front-End Lead

Tekskills Inc.; Bengaluru; Presencial; INR 2 000 000 - 4 000 000; Tempo integral

Resumo da oferta

Tekskills Inc. seeks a Digital Front-End Lead to drive chip-level architecture, RTL design, and verification while mentoring a high-performing team.

The role requires deep technical expertise and leadership across SoC design, RTL coding, verification planning, and project management. The candidate will lead verification strategies and collaborate with backend and analog teams, ensuring robust verification while contributing to architectural decisions.

Qualificações

• Experience with MCU products featuring ARM cores is preferred.
• Target products are not FPGA-based.

Responsabilidades

• Drive and contribute to chip-level architecture, RTL design, and verification, while mentoring a high-performing team.
• Provide leadership in verification strategy and collaborate across disciplines.
• Mentor and manage the Verification Leader with design exposure.

Conhecimentos

Chip Level Verification

Chip-Level Use Case Understanding

Verification Plan Formulation,

Extraction of verification items and

Building Dynamic & Static Verification

Gate-Level Simulation with Back-Annot

Management

Leadership Experience, ProjectPlanning

DFE Team Management

Documentation

Continuous Improvement Suggestions

Functional Safety Standards

RTL Design & Quality Verification

RTL Coding Skills (Verilog HDL/System

RTL Quality Check Execution; EDA Tools

Architecture Design

Chip-Level System Architecture Design

Block-level microarchitecture design

Constraint Creation and Synthesis (SDC

Timing and synthesis constraints

Synthesis trial and STA report

Chip-Level Assembly Using EDA Tools

Power System Design

Multi-Power Domain Design

Power System Model Design

Testing, On-Board Evaluation, and Mass

Evaluation Flow (Actual Machine Bring-

Evaluation Specifications (test items

Power Analysis Using EDA Tools and

Power Estimation During Feasibility

Ferramentas

EDA Tools

Descrição da oferta de emprego

Role & responsibilities

Job Summary

We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.

This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.

Key Skills - Priority Level (1-5)

• Chip Level Verification 5
• Chip-Level Use Case Understanding
• Verification Plan Formulation, Management, and Review
• Extraction of verification items and formulation of verification program stimulus specifications
• Building Dynamic & Static Verification Environments
• Gate-Level Simulation with Back-Annotated Delays
• Management -5
• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team
• DFE Team Management
• Documentation
• Continuous Improvement Suggestions
• Functional Safety Standards
• RTL Design & Quality Verification - 4
• RTL Quality Control
• RTL Coding Skills (Verilog HDL/System Verilog)
• RTL Quality Check Execution; EDA Tools for RTL Quality Checks
• Architecture Design 3
• Chip-Level System Architecture Design
• Block-level microarchitecture design
• Constraint Creation and Synthesis (SDC/STA) - 3
• Timing and synthesis constraints
• Synthesis trial and STA report confirmation
• Chip Level Assembly 3
• Chip-Level Assembly Using EDA Tools
• Power System Design- 3
• Multi-Power Domain Design
• Power System Model Design
• Testing, On-Board Evaluation, and Mass Production Support- 3
• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)
• Power Estimate- 2
• Power Analysis Using EDA Tools and Design Feedback
• Power Estimation During Feasibility Stage

Preferred candidate profile

xperience with MCU products featuring ARM cores is preferred. *

* Target products are not FPGA-based.*