Design Engineer

Tekskills Inc.; Kolkata District; Presencial; INR 4 000 000 - 7 000 000; Tempo integral

Resumo da oferta

Tekskills Inc. is seeking a Digital Front End Lead with 8-15 years of experience to drive chip-level verification and architecture decisions. The candidate will lead a high-performing team, mentor engineers, and collaborate across disciplines, emphasizing verification strategies and design input.

Experience with ARM cores and MCU-based products is preferred. The role covers RTL design, architecture design, power modeling, and mass production support, with a focus on robust verification

Qualificações

• 8-15 years of experience in digital front-end/RTL design and verification.
• Experience as a verification leader with design exposure.
• Experience with MCU products featuring ARM cores is preferred.

Responsabilidades

• Chip-Level Verification: understand use cases, formulate verification plans, extract stimuli, build dynamic and static environments, gate-level simulation with back-annotated delays.
• Management: lead teams, plan projects, collaborate with backend and analog teams.
• DFE Team Management: documentation, continuous improvement, adherence to functional safety standards.
• RTL Design & Quality Verification: RTL coding in Verilog/SystemVerilog, RTL quality checks with EDA tools.
• Architecture Design: chip-level system design and block-level microarchitecture.
• Constraint Creation & Synthesis: timing constraints and STA/SDC checks.
• Chip Level Assembly: assemble chip designs using EDA tools.
• Power System Design: multi-power domain design and modeling.
• Testing & Mass Production Support: evaluation flow, ATE patterns, and test specification.
• Power Estimate: power analysis and estimation feedback.

Conhecimentos

Leadership

Project management

Mentoring

Collaboration

Ferramentas

EDA tools

Verilog/SystemVerilog

Descrição da oferta de emprego

We are hiring for Digital Front End Lead

Job Title: Digital Front-End Lead Work

Experience: 8-15 years

• We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.
• This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.* Target products are not FPGA-based.*** Experience with MCU products featuring ARM cores is preferred. *

Chip Level Verification

• Chip-Level Use Case Understanding
• Verification Plan Formulation, Management, and Review
• Extraction of verification items and formulation of verification program stimulus specifications
• Building Dynamic & Static Verification Environments
• Gate-Level Simulation with Back-Annotated Delays

Management

• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team

DFE Team Management

• Documentation
• Continuous Improvement Suggestions
• Functional Safety Standards

RTL Design & Quality Verification

• RTL Quality Control
• RTL Coding Skills (Verilog HDL/System Verilog)
• RTL Quality Check Execution; EDA Tools for RTL Quality Checks

Architecture Design

• Chip-Level System Architecture Design
• Block-level microarchitecture design

Constraint Creation and Synthesis (SDC/STA)

• Timing and synthesis constraints
• Synthesis trial and STA report confirmation

Chip Level Assembly

• Chip-Level Assembly Using EDA Tools

Power System Design

• Multi-Power Domain Design
• Power System Model Design

Testing, On-Board Evaluation, and Mass Production Support

• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)

Power Estimate

• Power Analysis Using EDA Tools and Design Feedback
• Power Estimation During Feasibility Stage