Frontend Designer

Tekskills Inc.; Chennai; Vor Ort; INR 1.500.000 - 2.300.000; Vollzeit

Zusammenfassung

Tekskills Inc. is seeking an experienced IC Front-End Lead to drive chip-level verification and architecture decisions. You will lead and mentor a high-performing team, formulate verification plans, and collaborate across RTL, design, and backend teams.

The role emphasizes verification leadership, with exposure to architecture and chips, and requires strong project planning and collaboration skills. On-site Bangalore location.

Qualifikationen

• Chip-level verification with RTL/design exposure.
• Experience leading verification teams and defining verification plans.
• Knowledge of architecture, design decisions and project management.

Aufgaben

• Lead chip-level verification and develop verification programs.
• Mentor and manage DFE team and collaborate with RTL/design teams.
• Define timing constraints and synthesis checks; ensure quality verification.
• Drive architecture design and chip-level system understanding.
• Oversee power design, multi-power domain and test evaluation.

Kenntnisse

Verilog HDL

SystemVerilog

RTL Design

Chip-Level Verification

Leadership

Project Planning

DFE Management

Power Integrity

Verification Plan

Tools

EDA Tools

Timing/STA

Jobbeschreibung

Hi

We are hiring for IC Front-End Lead

Job Title: IC Front-End Lead
Work Location: Bangalore
Experience: 8-15 years of exp

Job Description:

We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.

This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.

* Target products are not FPGA-based.*

* Experience with MCU products featuring ARM cores is preferred. *

• Chip Level Verification
• Chip-Level Use Case Understanding
• Verification Plan Formulation, Management, and Review
• Extraction of verification items and formulation of verification program stimulus specifications
• Building Dynamic & Static Verification Environments
• Gate-Level Simulation with Back-Annotated Delays
• Management
• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team
• DFE Team Management
• Documentation
• Continuous Improvement Suggestions
• Functional Safety Standards
• RTL Design & Quality Verification
• RTL Quality Control
• RTL Coding Skills (Verilog HDL/System Verilog)
• RTL Quality Check Execution; EDA Tools for RTL Quality Checks
• Architecture Design
• Chip-Level System Architecture Design
• Block-level microarchitecture design
• Constraint Creation and Synthesis (SDC/STA)
• Timing and synthesis constraints
• Synthesis trial and STA report confirmation
• Chip Level Assembly
• Chip-Level Assembly Using EDA Tools
• Power System Design
• Multi-Power Domain Design
• Power System Model Design
• Testing, On-Board Evaluation, and Mass Production Support
• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)
• Power Estimate
• Power Analysis Using EDA Tools and Design Feedback
• Power Estimation During Feasibility Stage

Regards,

Sri Lakshmi