Design Engineer

Tekskills Inc.; Chennai; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Tekskills Inc. seeks an experienced Digital Front-End Lead to drive chip-level architecture, RTL design, and verification while mentoring a high-performing team.

The role emphasizes leadership across integration, verification planning, and project management with a focus on MCU products and ARM cores. The candidate will contribute to architecture decisions, oversee verification environments, and collaborate with backend and analog teams to ensure robust, scalable SoC designs.

Qualifications

• Experience leading chip-level front-end, RTL, and verification efforts.
• Proven ability to mentor teams and drive architectural decisions.
• Strong background in SoC design, RTL coding, verification planning, and project management.

Responsibilities

• Lead chip-level verification strategy and architecture decisions.
• Drive RTL design, verification environments, and quality checks.
• Mentor and manage a high-performing DFE team across multiple projects.
• Oversee architecture design and block-level microarchitecture.
• Create timing constraints and guide synthesis (SDC/STA) activities.
• Coordinate chip-level assembly and power system design considerations.
• Support testing, bring-up, and mass production readiness.

Skills

RTL Design

Verilog HDL

SystemVerilog

Digital Front-End

Leadership

Project Management

Mentoring

Chip-level Architecture

Verification Planning

Tools

EDA Tools

Gate-Level Simulation

Synthesis Constraints

Back-Annotated Delays

Job description

We are hiring for Digital Front End Lead

Job Title: Digital Front-End Lead Work

Experience: 8-15 years

• We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.
• This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.* Target products are not FPGA-based.*** Experience with MCU products featuring ARM cores is preferred. *

Chip Level Verification

• Chip-Level Use Case Understanding
• Verification Plan Formulation, Management, and Review
• Extraction of verification items and formulation of verification program stimulus specifications
• Building Dynamic & Static Verification Environments
• Gate-Level Simulation with Back-Annotated Delays

Management

• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team

DFE Team Management

• Documentation
• Continuous Improvement Suggestions
• Functional Safety Standards

RTL Design & Quality Verification

• RTL Quality Control
• RTL Coding Skills (Verilog HDL/System Verilog)
• RTL Quality Check Execution; EDA Tools for RTL Quality Checks

Architecture Design

• Chip-Level System Architecture Design
• Block-level microarchitecture design

Constraint Creation and Synthesis (SDC/STA)

• Timing and synthesis constraints
• Synthesis trial and STA report confirmation

Chip Level Assembly

• Chip-Level Assembly Using EDA Tools

Power System Design

• Multi-Power Domain Design
• Power System Model Design

Testing, On-Board Evaluation, and Mass Production Support

• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)

Power Estimate

• Power Analysis Using EDA Tools and Design Feedback
• Power Estimation During Feasibility Stage