DFT Technical Architect_Bengaluru

Eximietas Design; Bengaluru; On-site; INR 11,472,000 - 14,340,000; Full time

Benefits offered by this job

Cutting-edge semiconductor designs

Collaborative environment

Competitive compensation

Professional growth

Job summary

Eximietas Design in the USA is seeking a hands-on Design for Test (DFT) professional to lead end-to-end DFT flows from RTL to final pattern sign-off. You will own the DFT architecture, perform scan insertion and ATPG generation, and ensure robust test coverage across IP, subsystems, and SOCs.

The role requires block- and SOC-level pattern retargeting, DRC analysis, and integration of MBIST/IJTAG, with close collaboration across design, verification, and physical design teams.

Qualifications

• Strong experience with netlist handling and ATPG simulations.
• Proven expertise in block-level and SOC-level pattern retargeting and debugging.
• In-depth understanding of ICL and PDL standards.

Responsibilities

• End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
• Scan architecture definition and RTL/gate-level implementation including EDT and OCC.
• Execution of block-level ATPG, DRC analysis, and coverage optimization.
• Handling of pattern simulations (timing and non-timing).
• SOC-level integration including pattern retargeting to subsystem and full-chip levels.
• Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).
• Independent debugging of DFT simulations and netlist issues.
• Collaborate with design, verification, and physical design teams to ensure DFT readiness.
• Ownership of DFT sign-off activities and deliverables.

Skills

Netlist handling

ATPG simulations

Pattern retargeting

ICL & PDL standards

DFT tools (Synopsys TestMAX/TetraMAX)

DFT tools (Cadence Modus)

Tools

Synopsys TestMAX / TetraMAX

Cadence Modus

SSN

IJTAG / Boundary Scan

Job description

Locations : USA

San Jose (Bay Area) & Austin, USA.

• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether

you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles

that will challenge and grow your skills in advanced silicon testing.

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across

complex IP, subsystem, and SOC designs.

Core Responsibilities:

End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

Scan architecture definition and implementation at RTL and gate level, including EDT and

OCC.

Execution of block-level ATPG, DRC analysis, and coverage optimization.

Handling of pattern simulations, including both timing and non-timing simulations.

SOC-level integration, including pattern retargeting to subsystem and full-chip levels.

Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).

Independent debugging of DFT simulations and netlist-related issues.

Close collaboration with design, verification, and physical design teams to ensure DFT

readiness.

Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:

Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.

Perform scan insertion, ATPG generation, and pattern validation at block and top levels.

Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.

Define and execute DFT strategies aligned with project requirements and schedules.

Support pre-silicon and post-silicon test requirements.

Serve as the DFT point of contact for assigned projects, responsible for verification and test

readiness sign-off.

Technical Requirements:

Must-Have Skills:

Strong experience in netlist handling and ATPG simulations.

Proven expertise in block-level and SOC-level pattern retargeting and debugging.

In-depth understanding of ICL and PDL standards.

Hands-on experience with at least one major DFT tool suite:

o Synopsys TestMAX / TetraMAX

o Cadence Modus

Preferred & Advanced Skills:

Experience with Streaming Scan Network (SSN).

Knowledge of Analog and Mixed-Signal DFT methodologies.

Proficiency with SpyGlass for DFT linting and early-stage analysis.

Exposure to RTL-level DFT insertion and validation.

What We Offer:

• Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
• Collaborative and inclusive work environment.
• Competitive compensation and benefits package.
• Professional growth and development opportunities.

Best regards,

Associate VLSI Manager - Talent Acquisition | Visakhapatnam