Senior Director – DFT_Bengaluru

Eximietas Design; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Eximietas Design in Bengaluru seeks a Design for Test (DFT) professional to own the end-to-end DFT flow from RTL to final pattern delivery across complex IP, Subsystem, and SoC designs.

The role requires expertise in scan insertion, EDT & OCC, ATPG, DRC analysis, coverage closure, and MBIST/JTAG integration, with collaboration across Design, Verification, and Physical Design teams.

Qualifications

• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Experience with ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.

Responsibilities

• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.

Skills

End-to-End DFT Flow

Scan Insertion

ATPG

SoC Integration

MBIST

IJTAG

JTAG Implementation

Tools

Tessent

TestMAX/TetraMAX

Modus

Job description

Locations:

• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.

Key Skills:

• End-to-End DFT Flow Ownership.


• Scan Insertion, EDT & OCC.


• ATPG, DRC Analysis & Coverage Closure.


• SoC Integration & Pattern Retargeting.


• MBIST, IJTAG & JTAG Implementation.


• DFT Sign-off Activities.

Preferred Skills:

• Streaming Scan Network (SSN).

Core Responsibilities:

• End-to-end ownership of DFT implementation flow from RTL to sign-off.


• Scan architecture implementation including EDT & OCC.


• ATPG, DRC analysis, coverage optimization, and pattern simulations.


• SoC integration, pattern retargeting, and DFT debugging.


• MBIST, IJTAG, and Boundary Scan (JTAG) integration.


• Collaboration with Design, Verification, and Physical Design teams.


• DFT sign-off ownership and deliverables.

Technical Requirements:

• Strong experience in ATPG simulations and netlist handling.


• Expertise in block-level and SoC-level pattern retargeting/debugging.


• Strong understanding of ICL and PDL standards.


• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.

Best Regards,

Associate VLSI Manager – Talent Acquisition | Visakhapatnam