DFT Technical Architect_Hyderabad

Eximietas Design; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Eximietas Design in India is seeking experienced Design for Test (DFT) professionals to join our growing VLSI team, focusing on advanced silicon testing and SoC design. You will own end-to-end DFT flow from RTL to pattern sign-off across complex IP, subsystem, and SoC designs, drive DFT sign-off activities, and work with design, verification and physical design teams to deliver robust test solutions.

Join a fast-paced environment with opportunities to work on cutting-edge semiconductor

Qualifications

• Strong expertise in netlist handling and ATPG simulations.
• Experience with block-level and SoC-level pattern retargeting.
• Understanding of ICL and PDL standards.
• Hands-on experience with DFT tool suites such as Synopsys TestMAX / TetraMAX and Cadence Modus.

Responsibilities

• Own the end-to-end DFT flow from RTL to pattern sign-off.
• Define and implement scan architectures including EDT and OCC.
• Perform block-level ATPG, DRC analysis, and coverage optimization.
• Execute pattern simulations (timing and non-timing).
• Handle SoC-level integration and pattern retargeting.
• Integrate and debug MBIST, IJTAG, and Boundary Scan (JTAG).
• Debug DFT simulations and netlist-related issues.
• Collaborate with design, verification, and physical design teams.
• Drive DFT sign-off activities and project deliverables.

Skills

Netlist handling

ATPG simulations

Block-level pattern retargeting

SoC-level pattern retargeting

ICL and PDL standards

Tools

Synopsys TestMAX / TetraMAX

Cadence Modus

SpyGlass

Streaming Scan Network (SSN)

Job description

Greetings from Eximietas Design!

We are looking for experienced Design for Test (DFT) professionals to join our growing VLSI team. If you are passionate about advanced silicon testing and SoC design, this is a great opportunity to work on complex IP, Subsystem, and SoC level projects.

Locations:

• India:

USA Eligibility:

• USA: San Jose (Bay Area) / Austin
• U.S. Permanent Residents (Green Card holders) only

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SoC designs.

• Own the complete DFT implementation flow from RTL to pattern sign-off
• Define and implement scan architectures including EDT and OCC
• Perform block-level ATPG, DRC analysis, and coverage optimization
• Execute pattern simulations (timing and non-timing)
• Handle SoC-level integration and pattern retargeting
• Integrate and debug MBIST, IJTAG, and Boundary Scan (JTAG)
• Debug DFT simulations and netlist-related issues
• Collaborate closely with design, verification, and physical design teams
• Drive DFT sign-off activities and project deliverables

Must-Have Skills

• Strong expertise in netlist handling and ATPG simulations
• Experience with block-level and SoC-level pattern retargeting
• Understanding of ICL and PDL standards
• Hands-on experience with DFT tool suites such as:
• Synopsys TestMAX / TetraMAX
• Cadence Modus

Preferred Skills

• Experience with Streaming Scan Network (SSN)
• Knowledge of Analog & Mixed-Signal DFT methodologies
• Exposure to SpyGlass for DFT linting
• Experience in RTL-level DFT insertion

Work on cutting-edge semiconductor and SoC technologies

Opportunity to collaborate with top industry experts

Strong career growth opportunities

Best Regards,