Principal SoC DFT Engineer_Bengaluru

Eximietas Design; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Benefits offered by this job

Cutting-edge semiconductor designs

Collaborative work environment

Competitive compensation and benefits

Professional growth opportunities

Job summary

Eximietas Design seeks an experienced Design for Test (DFT) professional with 10+ years to lead end-to-end DFT flows in Bengaluru. You will own RTL-to-pattern sign-off, scan insertion, ATPG, and pattern validation, while coordinating with design and verification teams to ensure robust DFT readiness.

You will work with advanced DFT tool suites and retargeting at block and SOC levels, contributing to cutting-edge semiconductor testing efforts and pre/post-silicon test strategies.

Qualifications

• Must have hands-on experience with netlist handling and ATPG simulations.
• Proven expertise in block-level and SOC-level pattern retargeting and debugging.
• In-depth understanding of ICL and PDL standards.
• Hands-on experience with at least one major DFT tool suite: Synopsys TestMAX / TetraMAX or Cadence Modus.

Responsibilities

• End-to-end ownership of the DFT flow from RTL to final pattern sign-off.
• Scan architecture definition and implementation at RTL and gate level, including EDT and OCC.
• Execute block-level ATPG, DRC analysis, and coverage optimization.
• Handle pattern simulations (timing and non-timing).
• SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
• Integrate, simulate and debug MBIST, IJTAG and Boundary Scan (JTAG).
• Collaborate with design, verification and physical design teams to ensure DFT readiness.

Skills

Netlist handling

ATPG simulations

Block-level DFT

SOC-level retargeting

ICL standards

PDL standards

DFT tools

Tools

Synopsys TestMAX

TetraMAX

Cadence Modus

Job description

Experience: Min 10+Years.

• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether

you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles

that will challenge and grow your skills in advanced silicon testing.

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across

complex IP, subsystem, and SOC designs.

Core Responsibilities:

End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

Scan architecture definition and implementation at RTL and gate level, including EDT and

OCC.

Execution of block-level ATPG, DRC analysis, and coverage optimization.

Handling of pattern simulations, including both timing and non-timing simulations.

SOC-level integration, including pattern retargeting to subsystem and full-chip levels.

Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).

Independent debugging of DFT simulations and netlist-related issues.

Close collaboration with design, verification, and physical design teams to ensure DFT

readiness.

Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:

Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.

Perform scan insertion, ATPG generation, and pattern validation at block and top levels.

Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.

Define and execute DFT strategies aligned with project requirements and schedules.

Support pre-silicon and post-silicon test requirements.

Serve as the DFT point of contact for assigned projects, responsible for verification and test

readiness sign-off.

Technical Requirements:

Must-Have Skills:

Strong experience in netlist handling and ATPG simulations.

Proven expertise in block-level and SOC-level pattern retargeting and debugging.

In-depth understanding of ICL and PDL standards.

Hands-on experience with at least one major DFT tool suite:

o Synopsys TestMAX / TetraMAX

o Cadence Modus

Preferred & Advanced Skills:

Experience with Streaming Scan Network (SSN).

Knowledge of Analog and Mixed-Signal DFT methodologies.

Proficiency with SpyGlass for DFT linting and early-stage analysis.

Exposure to RTL-level DFT insertion and validation.

What We Offer:

• Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
• Collaborative and inclusive work environment.
• Competitive compensation and benefits package.
• Professional growth and development opportunities.

Referrals are highly appreciated.

Best regards,

Associate VLSI Manager - Talent Acquisition | Visakhapatnam