Senior DFT Managers_Hyderabad

Eximietas Design; Hyderabad; Hybrid; INR 3,500,000 - 6,500,000; Full time

Benefits offered by this job

Cutting-edge projects

Collaborative environment

Competitive compensation

Professional growth

Job summary

Eximietas Design is seeking an experienced Design for Test (DFT) professional with 15+ years background to drive end-to-end DFT flows from RTL to pattern sign-off across IP, subsystem, and SOC designs. The role emphasizes architecture, ATPG, and advanced DFT techniques in a challenging silicon testing environment.

You will collaborate with design, verification, and physical teams to ensure readiness for pre- and post-silicon testing, while leveraging tools like Synopsys TestMAX, TetraMAX, and

Qualifications

• Must have extensive experience in netlist handling and ATPG simulations.
• Expertise in block- and SOC-level pattern retargeting and debugging.
• Strong knowledge of ICL and PDL standards.
• Hands-on experience with major DFT tool suites (TestMAX/TetraMAX, Modus).

Responsibilities

• End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
• Scan architecture definition at RTL and gate level, including EDT and OCC.
• Execute block-level ATPG, DRC analysis, and coverage optimization.
• Handle pattern simulations, timing and non-timing.
• Integrate DFT at SOC level and retarget patterns to subsystems and full-chip.
• Integrate, simulate, and debug MBIST, IJTAG, and Boundary Scan.
• Debug DFT simulations and netlist-related issues independently.
• Collaborate with design, verification, and physical design teams for DFT readiness.
• Own DFT sign-off activities and deliverables.
• Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
• Perform scan insertion, ATPG generation, and pattern validation at block/top levels.
• Analyze and resolve coverage, DRC, and simulation failures to meet targets.
• Define and execute DFT strategies aligned with project requirements.
• Support pre-silicon and post-silicon test requirements.
• Serve as DFT point of contact for assigned projects.

Skills

Netlist handling

ATPG simulations

Block-level pattern retargeting

SOC-level pattern retargeting

ICL/PDL standards

Tools

Synopsys TestMAX

TetraMAX

Cadence Modus

Job description

Experience: Min 15+Years.

• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether

you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles

that will challenge and grow your skills in advanced silicon testing.

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across

complex IP, subsystem, and SOC designs.

Core Responsibilities:

End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

Scan architecture definition and implementation at RTL and gate level, including EDT and

OCC.

Execution of block-level ATPG, DRC analysis, and coverage optimization.

Handling of pattern simulations, including both timing and non-timing simulations.

SOC-level integration, including pattern retargeting to subsystem and full-chip levels.

Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).

Independent debugging of DFT simulations and netlist-related issues.

Close collaboration with design, verification, and physical design teams to ensure DFT

readiness.

Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:

Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.

Perform scan insertion, ATPG generation, and pattern validation at block and top levels.

Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.

Define and execute DFT strategies aligned with project requirements and schedules.

Support pre-silicon and post-silicon test requirements.

Serve as the DFT point of contact for assigned projects, responsible for verification and test

readiness sign-off.

Technical Requirements:

Must-Have Skills:

Strong experience in netlist handling and ATPG simulations.

Proven expertise in block-level and SOC-level pattern retargeting and debugging.

In-depth understanding of ICL and PDL standards.

Hands-on experience with at least one major DFT tool suite:

• Synopsys TestMAX / TetraMAX
• Cadence Modus

Preferred & Advanced Skills:

Experience with Streaming Scan Network (SSN).

Knowledge of Analog and Mixed-Signal DFT methodologies.

Proficiency with SpyGlass for DFT linting and early-stage analysis.

Exposure to RTL-level DFT insertion and validation.

What We Offer:

• Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
• Collaborative and inclusive work environment.
• Competitive compensation and benefits package.
• Professional growth and development opportunities.