DFT Engineers

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru seeks an experienced DFT Engineer to drive Design-for-Test activities, including scan insertion, ATPG, and OCC integration. The role focuses on debugging DFT flows and improving test coverage across multiple modes and scenarios.

The candidate will work with SSN, IJTAG, ICL, and PDL frameworks, analyzing complex issues and delivering structured debug solutions within a collaborative, cross-functional team environment.

Qualifications

• DFT fundamentals focus including ATPG, scan architecture, and OCC.
• DRC debug and coverage debug across modes.
• Simulation debugging across various scenarios in DFT flow.

Responsibilities

• Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
• OCC integration
• Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
• Analyze and resolve issues related to testability, fault coverage, and pattern generation
• Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
• Collaborate with cross-functional teams to ensure smooth DFT integration and issue resolution
• Contribute to continuous improvement of DFT flows, methodologies, and debug

Skills

DFT basics

ATPG

Scan architecture

OCC

Debug: DRC

Debug: coverage

Debug: simulation

SSN

IJTAG

ICL

PDL handling

Structured debugging

Job description

NOTE: Immediate candidates are preferred.

Key Responsibilities

• Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and
• OCC integration
• Perform DRC debug, test coverage analysis, and simulation debug across various stages
• of the DFT flow
• Analyze and resolve issues related to testability, fault coverage, and pattern generation
• Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
• Collaborate with cross-functional teams to ensure smooth DFT integration and issue
• Contribute to continuous improvement of DFT flows, methodologies, and debug

Required Skills & Experience

• Strong understanding of DFT fundamentals including ATPG, scan architecture, and OCC
• DRC debug, Coverage debug,Simulation debug (various modes and scenarios)
• Exposure to SSN, IJTAG, ICL, and PDL frameworks
• Ability to analyze complex issues and provide structured debug solutions