DFT Engineer - Hyderabad

N Human Resources & Management Systems; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

N Human Resources & Management Systems in Hyderabad is seeking a DFT Engineer to join the VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

You will lead a small team and collaborate with RTL, Physical Design, and STA groups to drive testability closure and robust manufacturing readiness for each silicon tapeout.

Qualifications

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST).
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools.
• Comprehensive understanding of test coverage, pattern generation, and silicon debug.

Responsibilities

• Handle scan insertion, ATPG pattern generation, and fault coverage analysis.
• Define and implement MBIST/LBIST architecture for memory and logic test.
• Develop boundary scan and DFT-aware constraints; perform scan chain stitching and test point insertion.
• Debug silicon test failures and correlate with simulations; mentor a team of 3–4 DFT engineers.
• Collaborate with RTL, Physical Design, and STA teams for testability closure.

Skills

DFT

ATPG

Scan

MBIST/LBIST

Test coverage

Leadership

Tools

Tessent

DFTMax

Job description

N Human Resources & Management Systems | Full time

We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key Responsibilities:

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Requirements:

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools
• Comprehensive understanding of test coverage, pattern generation, and silicon debug