DFT Engineer

HCLTech; Ernakulam; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

HCLTech is seeking a highly accomplished Design for Testability (DFT) Engineer to lead DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands mastery of DFT methodologies and the ability to drive the implementation of robust test strategies.

You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred).
• Minimum of 12 to 20 years of experience in Design for Testability (DFT) for complex ASICs and SoCs.
• Proven track record of leading and implementing DFT strategies for high-volume production.
• In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.).
• Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.) and scripting languages (Perl, TCL) for automation.

Responsibilities

• Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization.
• Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques.
• Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates.
• Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization.
• Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team.
• Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality.
• Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies.
• Manage and maintain DFT libraries and internal DFT standards.
• Contribute to the continuous improvement of the DFT flow within the team.

Skills

DFT Strategy

Leadership

ATPG/Scan Insertion

Boundary Scan

Scripting (Perl TCL)

DFT Tools

Manufacturing Test

Education

Master's degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Synopsys DFT Compiler

TetraMAX

Perl

TCL

Job description

Job Summary:

We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.

Responsibilities:

• Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization
• Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques
• Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates
• Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization
• Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team
• Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality
• Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies
• Manage and maintain DFT libraries and internal DFT standards
• Contribute to the continuous improvement of the DFT flow within the team

Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
• Minimum of 12 to 20 years of experience in Design for Testability (DFT) for complex ASICs and SoCs
• Proven track record of successfully leading and implementing DFT strategies for high-volume production
• In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.)
• Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.) and scripting languages (Perl, TCL) for automation
• Strong understanding of digital design principles (combinational logic, sequential logic) and manufacturing test processes
• Excellent analytical and problem-solving skills with a focus on achieving optimal test quality and cost-effectiveness
• Effective leadership, communication, collaboration, and teamwork skills