Design for Testability Lead

HCLTech; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

HCLTech in Bengaluru is seeking a senior Design for Testability (DFT) Engineer to lead DFT efforts for complex ASIC and SoC projects. This role demands mastery of DFT methodologies and the ability to drive robust test strategies for manufacturability and high test quality.

You will define DFT strategy, collaborate with design/verification teams, mentor engineers, and stay ahead with emerging tools and methods in a dynamic, growth-oriented environment.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field (highly preferred).
• Minimum of 10+ years of experience in Design for Testability (DFT) for complex ASICs and SoCs.
• Proven track record of leading and implementing DFT strategies for high-volume production.
• Expertise in DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability/Power).

Responsibilities

• Lead and define the overall DFT strategy for assigned projects, focusing on manufacturability and cost optimization.
• Collaborate with design and verification teams to integrate DFT techniques throughout the design flow.
• Develop and implement advanced DFT methodologies to achieve high test coverage and fault detection rates.
• Champion best practices for DFT and participate in design reviews, providing guidance on feasibility and optimization.
• Lead and mentor junior DFT engineers, fostering excellence and knowledge sharing.
• Analyze test results, identify design issues, and recommend corrective actions for high test quality.
• Stay updated on emerging DFT tools and methodologies and drive adoption.
• Manage and maintain DFT libraries and internal standards.
• Contribute to continuous improvement of the DFT flow within the team.

Skills

DFT strategy leadership

ATPG & Scan

Boundary Scan

Automation scripting

Education

Master's degree in Electrical Engineering

Tools

Synopsys DFT Compiler

TetraMAX

Job description

We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.

Responsibilities:

• Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization
• Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques
• Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates
• Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization
• Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team
• Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality
• Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies
• Manage and maintain DFT libraries and internal DFT standards
• Contribute to the continuous improvement of the DFT flow within the team

Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
• Minimum of 10+ years of experience in Design for Testability (DFT) for complex ASICs and SoCs
• Proven track record of successfully leading and implementing DFT strategies for high-volume production
• In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.)
• Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.) and scripting languages (Perl, TCL) for automation
• Strong understanding of digital design principles (combinational logic, sequential logic) and manufacturing test processes
• Excellent analytical and problem-solving skills with a focus on achieving optimal test quality and cost-effectiveness
• Effective leadership, communication, collaboration, and teamwork skills
• Competitive salary and benefits package commensurate with experience and expertise
• Opportunity to lead and influence the DFT strategy for cutting-edge technologies
• Dynamic and challenging work environment with opportunities for professional growth and leadership development
• Recognition and rewards for outstanding contributions