DFT Engineer

Capgemini; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Capgemini Bengaluru is seeking an experienced DFT Architect to lead the DFT architecture and test strategy for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.

The role requires defining ATPG, scan, MBIST/LBIST strategies, driving coverage objectives, and collaborating with RTL, Verification, and Physical Design teams across complex tapeouts.

Qualifications

• 12+ years of DFT experience in advanced SoCs.
• Experience defining DFT architecture and test strategies for complex chips.
• Strong knowledge of ATPG, scan, MBIST/LBIST approaches.
• Hands-on with DFT tools such as Tessent and Synopsys.

Responsibilities

• Define SoC DFT architecture.
• Establish ATPG, scan, MBIST, LBIST strategies.
• Drive test coverage objectives.
• Define compression and diagnosis methodologies.
• Work with RTL, Verification, and Physical Design teams.
• Review DFT signoff requirements.
• Interface with customer test and manufacturing organizations.

Skills

DFT architecture

ATPG

MBIST/LBIST

Test compression

JTAG/IEEE 1500/1687

SoC tapeouts

Tessent

Synopsys DFT tools

Tools

Tessent

Synopsys DFT tools

Job description

Job Description

Lead DFT architecture and test strategy definition for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.

Job Description - Grade Specific

Key Responsibilities

• Define SoC DFT architecture.
• Establish ATPG, scan, MBIST, LBIST strategies.
• Drive test coverage objectives.
• Define compression and diagnosis methodologies.
• Work with RTL, Verification, and Physical Design teams.
• Review DFT signoff requirements.
• Interface with customer test and manufacturing organizations.

Must Have

• 12+ years of DFT experience.
• Multiple successful SoC tapeouts.
• Good Knowledge on RISC and ARM SoC DFT strategy for sub-systems and top level
• Expertise in scan insertion and ATPG.
• Strong understanding of MBIST/LBIST.
• Experience with Tessent and/or Synopsys DFT tools.
• Knowledge of test compression and diagnosis.
• Understanding of JTAG and IEEE 1500/1687.

Good to Have

• Safety DFT.
• Automotive test methodologies.
• Silicon bring-up support experience.
• Yield learning and diagnosis.
• Chiplet test architecture.
• Advanced node test challenges.