DFT Design Engineer - ASIC SoC

Sykatiya Technologies Pvt Ltd; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd is seeking a skilled DFT Engineer to join our ASIC/SoC design team in India. The candidate will implement DFT, generate ATPG patterns, and optimize test architecture for complex SoCs.

You will collaborate with RTL, Physical Design and Verification teams to ensure high test coverage, efficient silicon testing, and robust post-silicon support across Bangalore/Hyderabad. 3–8 years of hands-on DFT experience is expected.

Qualifications

• 3–8 years hands-on experience in DFT and ATPG.
• MBIST, scan insertion, scan compression and wrapper insertion knowledge.
• ATPG pattern generation, simulation and fault coverage analysis.
• Experience with flat and hierarchical SoC designs.
• JTAG and boundary scan understanding.
• Ability to create STA constraints for DFT modes.
• Collaborates with RTL, PD and verification teams.

Responsibilities

• Develop DFT strategies for complex ASIC/SoC designs.
• Plan MBIST architecture and insert MBIST elements.
• Plan and execute scan insertion and scan-chain configuration.
• Implement test compression and wrapper insertion for efficiency.
• Generate ATPG patterns and perform simulations & validations.
• Handle both flat and hierarchical SoCs with proper DFT integration.
• Work on JTAG and boundary scan architecture and issues.
• Create STA constraints for various DFT modes.
• Analyze DFT rule checks and resolve testability issues.
• Support timing, coverage and test quality through design cycle.

Skills

DFT implementation

ATPG patterns

MBIST planning

Scan insertion

Scan compression

Wrapper insertion

JTAG boundary scan

STA constraints

DFT architecture

Fault coverage

Cross-team collaboration

Job description

Job Description

Job Title : DFT Engineer

Experience : 3 - 8 Years

Location : Bangalore / Hyderabad

About The Role

We are seeking skilled Design for Testability (DFT) Engineers to join our ASIC/SoC design team. The ideal candidate will have hands-on experience in DFT implementation, ATPG pattern generation, and test architecture development for complex SoC designs. The role involves collaborating with RTL Design, Physical Design, Verification, and Product Engineering teams to ensure high test coverage, improved test quality, and efficient silicon testing.

Key Responsibilities

• Develop and implement DFT strategies for complex ASIC/SoC designs.
• Perform MBIST planning, architecture definition, and insertion.
• Execute scan architecture planning, scan insertion, and scan-chain configuration.
• Implement test compression and wrapper insertion for improved test efficiency.
• Generate ATPG patterns and perform ATPG simulations and pattern validation.
• Handle both flat and hierarchical SoC designs, ensuring effective DFT integration.
• Work on JTAG implementation, IEEE 1149.1, and boundary scan architecture.
• Create and validate STA constraints for various DFT modes, including shift, capture, and test operations.
• Analyze DFT rule-checking (DRC) violations and resolve testability issues.
• Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
• Support timing, coverage, and test-quality optimization throughout the design cycle.
• Assist with post-silicon testing, silicon bring-up, and debugging of DFT-related issues.

Required Skills

• 3 - 8 years of hands-on experience in DFT implementation and ATPG activities.
• Strong knowledge of MBIST, scan insertion, scan compression, and wrapper insertion.
• Experience in ATPG pattern generation, simulation, and fault coverage analysis.
• Proficiency in handling flat and hierarchical SoC designs.
• Good understanding of JTAG, boundary scan, and DFT architecture.
• Experience in creating STA constraints for DFT modes.
• Knowledge of DFT rule checks, scan-chain debugging, and test coverage improvement.
• Familiarity with industry-standard DFT and ATPG tools.
• Strong problem-solving skills and the ability to collaborate across design teams.

(ref:hirist.tech)