DFT ATPG Engineer - 2290

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is hiring a DFT ATPG Engineer to join the Server SoC DFT team in Bengaluru. You will own ATPG deliverables, improve test pattern generation speed and quality, and contribute to coverage dashboards and debug workflows.

The role requires 3-5 years of relevant DFT ATPG experience, exposure to DFT architectures, and strong scripting skills to automate reports and analysis. This is a 1-year contract position in Bengaluru.

Qualifications

• 3-5 years of hands-on DFT ATPG experience in complex SoCs.
• Exposure to DFT architecture and design for SoCs.
• Strong knowledge of ATPG tools such as Mentor Tessent or equivalent.
• Exposure to static timing analysis and timing closure.
• Hands-on debugging with scripting and automation for test patterns and reports.

Responsibilities

• Own core ATPG deliverables for Server SoC DFT team.
• Improve speed, quality, and repeatability of test pattern generation.
• Develop and maintain coverage dashboards and quality gates.
• Automate reporting and debugging workflows using scripts and tools.

Skills

DFT ATPG

ATPG tools

Timing analysis

Debug & scripting

DFT reporting & dashboards

Tools

Mentor Tessent

TK

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position

DFT ATPG Engineer

Experience

3-5 Years

Location

Bengaluru

Contract tenure

1 year

Top 3 Skills

• Relevant exp in DFT ATPG should be 3+ Exposure to DFT architecture and design for complex SoCs.


• Good working knowledge of ATPG tools, including Mentor Tessent / TK or equivalent platforms.


• Exposure to static timing analysis and timing closure.


• Excellent hands-on debug ability and strong scripting skills.


• Experience building DFT reporting frameworks, coverage dashboards, or automated quality gates.

Role Summary

As a key member of the Server SoC DFT team, the successful candidate will play a significant role in ensuring the quality of next-generation SoCs through structural DFT, ATPG, LBIST, and execution-focused automation. In addition to owning core ATPG deliverables, this engineer will be expected to improve the speed, quality, and repeatability of manufacturing test pattern generation, coverage review, and debug closure by using strong scripting, reporting frameworks, and selective AI-assisted analysis.

Preferred Qualifications

• Experience building DFT reporting frameworks, coverage dashboards, or automated quality gates.


• Experience applying analytics or AI to coverage debug, diagnosis review, test-time optimization, or retargeting efficiency.


• Exposure to silicon data analysis, tester-readiness metrics, or manufacturing test cost optimization.


• Experience working with CAD, EDA vendor, or internal automation teams to productionize new flow capabilities.


• Post-silicon bring-up and failure-debug experience.