Senior Design Verification Engineer

ACL Digital; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading semiconductor recruiting firm in Bengaluru is looking for an experienced Design Verification Engineer with a focus on PCIe IP verification, SystemVerilog, and UVM. This full-time role demands strong skills in testbench development, debugging, and working with cross-functional teams. Candidates with over 6 years of experience in the semiconductor field are encouraged to apply via the provided contact email for enhanced interview opportunities.

Qualifications

• 6+ years of experience in verification processes.
• Hands-on experience in PCIe protocol and VIP.
• Excellent problem-solving and teamwork skills.

Responsibilities

• Develop SV/UVM testbenches and assertions.
• Create and review test plans for IP/Sub-system verification.
• Conduct coverage-driven verification and debugging.

Skills

PCIe IP verification

SystemVerilog

UVM

Debugging skills

Testing and coverage skills

Scripting (Python/Perl)

Job description

HR Executive TAG at ACL Digital || VLSI Recruiter || Hiring For DV\RTL\DFT\AL\ALD\PD Engineers

Experience: 6+ Yrs

We are looking for an experienced Design Verification Engineer with strong expertise in PCIe IP verification, SystemVerilog, and UVM.

Responsibilities

• Hands‑on experience in PCIe protocol, VIP, coverage‑driven verification & debugging
• Strong skills in SV/UVM testbench development, assertions, and scoreboarding
• Experience in IP/Sub‑system level verification, test plan creation & reviews
• Solid understanding of verification flows, regressions, and scripting (Python/Perl preferred)
• Excellent problem‑solving and ability to work with cross‑functional teams

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

Job Function

• Semiconductor Manufacturing

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Contact Email: [e-mail]