PCIe Verification (BB510FT RM 4464)

Source-Right; Hyderabad; Presencial; INR 1.800.000 - 3.000.000; Jornada completa

Descripción de la vacante

Source-Right in Hyderabad is seeking an experienced PCIe Verification engineer to lead IP/sub-system verification and design top-level test plans. You will develop UVM-based SV test-benches, apply verification methodologies, and contribute to quality metrics while collaborating with peers in a fast-paced environment.

The role requires strong debugging, problem-solving, and teamwork skills, with a focus on rigorous verification across PCIe IPs in an on-site Hyderabad setting.

Formación

• An expert level experience with PCIe IP/sub-systems.
• Defining block, sub-system and SOC top level test plans.
• Expert level with developing UVM-based SV test-benches.
• Deep understanding and knowledge of verification methodologies flows and quality metrics.
• Great debugging and problem-solving skills.
• Team player with great interpersonal communication skills.

Conocimientos

IP/Block/Subsystem Verification

SV/UVM Verification

Interfaces (AXI/AHB)

PCIe Protocols

Scripting (Perl/Python)

Educación

Bachelor's degree in EE/CS

Herramientas

ASIC simulators

Descripción del empleo

Position: PCIe Verification (BB510FT RM 4464)

Education: B.S. in electrical engineering, computer science with extensive industry experience.

Candidates must be comfortable with the Hyderabad location.

Job Requirements

• An expert level experience with PCIe IP/sub-systems.
• Highly experienced with defining block, sub-system and SOC top level test plans.
• An expert level with developing UVM-based SV test-benches.
• Deep understanding and knowledge of verification methodologies flows and quality metrics.
• Great debugging and problem-solving skills.
• Team player with great interpersonal communication skills.

Job Qualifications

• At least 5-10 years of relevant experience in Nand, DDR and PCIe verification.
• Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
• Expert level in verification languages such as UVM and System Verilog.
• Relevant experience with writing block-level and SoC test-plans.

Skills Required

• IP/Block/Subsystem Verification (RTL Front end verification) – minimum 5 years
• SV, UVM Verification – minimum 4 Years
• Interfaces (AXI/AHB) – minimum 2 years
• Protocols (PCIE) – minimum 2 years
• Scripting (Perl/Python) – Optional.