Design Verification Engineer

Tessolve; Khordha; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Tessolve Semiconductor in Bhubaneswar, Odisha, India is seeking experienced IP/SoC Verification Engineers to join our growing verification teams. You will work on functional verification at IP/SoC level, develop SystemVerilog/UVM based environments, and verify high-speed protocols.

Responsibilities include testbench development, debugging, coverage closure, and collaborating with design/architecture teams. A strong background in SystemVerilog, UVM, and protocols like PCIe, USB, Ethernet is

Qualifications

• 4–10 years of experience in IP/SoC verification.
• Strong hands-on experience with SystemVerilog & UVM.
• Experience with high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, SATA, HDMI, DisplayPort.

Responsibilities

• IP and SoC level functional verification.
• Development of SystemVerilog / UVM-based verification environments.
• Verification of high-speed protocols.
• Testbench development, test creation, and execution.
• Debugging simulation failures and protocol issues.
• Functional, code, and assertion coverage closure.
• Collaboration with design, architecture, and validation teams.
• Support regression, reviews, and verification sign-off.

Skills

IP/SoC Verification

SystemVerilog

UVM

High-speed Protocols

Debugging

Tools

SystemVerilog

UVM

Job description

Please find the below JD for IP and SOC.

Experience: 4–10Years

• Location: Bhubaneswar, Odisha, India

Company: Tessolve Semiconductor

We are looking for experienced IP / SoC Verification Engineers with strong hands-on exposure to high-speed interface protocols to join our growing verification teams.

Key Responsibilities

• IP and SoC level functional verification


• Development of SystemVerilog / UVM-based verification environments


• Verification of high-speed protocols


• Testbench development, test creation, and execution


• Debugging simulation failures and protocol issues


• Functional, code, and assertion coverage closure


• Collaboration with design, architecture, and validation teams


• Support regression, reviews, and verification sign-off

Mandatory Skills

• 4–10 years of experience in IP / SoC Verification


• Strong hands-on experience with SystemVerilog & UVM


• Experience with one or more high-speed protocols:


• PCIe, USB, Ethernet, DDR, MIPI (CSI/DSI), SATA, HDMI, DisplayPort


• Good understanding of SoC fundamentals (clocking, resets, interconnects)


• Experience with assertion-based verification (SVA)


• Strong debugging and problem-solving skills

Good to Have

• VIP integration and customization experience


• Low-power verification knowledge (UPF/CPF)