Design Verification Engineer

HCLTech; Ernakulam; On-site; INR 1,600,000 - 2,600,000; Full time

Job summary

HCLTech in Cochin (Kerala) seeks a VLSI Design Verification Engineer to validate complex ASIC/SoC/IP designs. You will develop scalable verification environments, create test plans, and ensure functional correctness using advanced methodologies like UVM.

You will collaborate with design, architecture, and physical design teams to deliver first-time-right silicon, leveraging SystemVerilog, PCIe protocol expertise, and automation of regression flows.

Qualifications

• Proficiency in SystemVerilog and UVM for ASIC/SoC verification.
• Experience with PCIe protocol and debugging across RTL and gate-level simulations.

Responsibilities

• Develop directed and constrained-random testcases
• Debug failures and root-cause issues across RTL, testbench, and tools
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

Skills

SystemVerilog

UVM

RTL debugging

Gate-level simulation

PCIe protocol

Education

B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Tools

VCS

Verdi

EDA tools

Job description

Job Title: VLSI Design Verification Engineer

Location - Cochin (Kerala)

Experience Level

4–15 years (can be adjusted based on hiring band)

Job Summary

We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon

Key Responsibilities

• Develop directed and constrained-random testcases
• Debug failures and root-cause issues across RTL, testbench, and tools
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

Required Skills & Qualifications

Technical Skills

• Good knowledge of SystemVerilog
• Hands-on experience with UVM (Universal Verification Methodology)
• Experience with EDA tools (e.g., VCS, Verdi)
• Experience in debugging RTL and gate level simulation issues
• Good knowledge of PCIe protocol

Education

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Soft Skills

• Strong analytical and debugging skills
• Good communication and cross-functional collaboration