Design Veification Engineer

Wipro; Hyderabad, Pune District, Bengaluru; Hybrid; INR 2,500,000 - 3,500,000; Full time

Job summary

Wipro is seeking a verification engineer to develop comprehensive PCIe verification plans for IP, sub-systems and SoCs. You will design reusable UVM environments, create directed and constrained-random test cases, and build scoreboards, monitors, and coverage models.

The role requires collaboration with RTL, architecture, and validation teams, participation in reviews and sign-off, and mentoring of junior engineers. PCIe exposure is mandatory for this position.

Qualifications

• Experience in PCIe verification for IP/Sub-system/SoC.
• Ability to design reusable UVM-based environments.
• Proficiency in directed and constrained-random test cases.

Responsibilities

• Develop and execute verification plans for PCIe IP/Sub-system/SoC.
• Create reusable UVM-based verification environments.
• Develop scoreboards, monitors, checkers, assertions, and coverage models.
• Perform protocol verification for PCIe Gen3/Gen4/Gen5/Gen6.
• Drive code and functional coverage closure.
• Collaborate with RTL, architecture, and validation teams.
• Participate in verification sign-off and reviews.
• Mentor junior engineers and review deliverables.

Skills

PCIe exposure

Verification planning

Testbench development

Collaboration

Tools

UVM

Scoreboards

Monitors

Assertions

Coverage tools

Job description

Role & responsibilities

Develop and execute comprehensive verification plans for PCIe IP/Sub-system/SoC.

Design and maintain reusable UVM-based verification environments.

Create directed and constrained-random test cases.

Develop scoreboards, monitors, checkers, assertions, and functional coverage models.

Perform protocol compliance verification for PCIe Gen3/Gen4/Gen5/Gen6.

Execute regression testing, debug failures, and perform root-cause analysis.

Drive code coverage and functional coverage closure.

Collaborate closely with RTL designers, architecture teams, and validation teams.

Participate in specification reviews and verification signoff activities.

Mentor junior engineers and review verification deliverables.

MANDATORY SKILLS

PCIE EXPOSURE IS MANDATORY. CANDIDATES WITHOUT PCIE EXPOSURE KINDLY REFRAIN.