Design for Test Engineers

Bibha AI Inc.; India; On-site; INR 1,200,000 - 3,000,000; Full time

Benefits offered by this job

Health insurance

Retirement plan

Paid time off

Training & development

Job summary

Tessolve is seeking skilled DFT Engineers with 4–10 years of experience to develop and implement advanced DFT methodologies for SoCs and ASICs. You will work across RTL, timing, and verification teams to ensure robust testability and silicon quality.

Join a team delivering high-quality test coverage, optimizing area, power, and performance, while supporting ATE patterns and silicon validation in a collaborative, fast-paced environment.

Qualifications

• Deep knowledge of DFT methodologies including Scan, ATPG, BIST, Boundary Scan.
• Hands-on experience with industry DFT EDA tools.
• Understanding of RTL, synthesis, timing, and verification.
• Strong debugging across pre-silicon and post-silicon phases.
• Experience with multi-million gate SoCs/ASICs.
• Scripting for automation (Perl, Python, Tcl, Shell).
• Excellent communication and teamwork.

Responsibilities

• Develop and implement DFT architectures for SoC/ASIC designs.
• Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan.
• Work on tool flows for Synopsys/Mentor/Cadence DFT tools.
• Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features.
• Debug and resolve issues during synthesis, simulation, and silicon bring-up.
• Deliver high-quality test coverage while optimizing for area, power, and performance impact.
• Support ATE patterns generation and silicon validation.

Skills

DFT methods

ATPG

Boundary Scan

JTAG

TCL scripting

Python scripting

RTL understanding

Team collaboration

Education

Bachelor's/Master's in ECE/EE

Tools

Synopsys DFTMAX

TetraMAX

Cadence Modus

Mentor Tessent

Job description

Company Overview

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide end-to-end solutions in VLSI Design, Test & Product Engineering, and Embedded Systems. We work with leading semiconductor companies worldwide, enabling innovation through deep domain knowledge and engineering excellence.

Summary of the Role

We are looking for skilled and motivated Design for Test (DFT) Engineers with 4-10 years of experience in developing and implementing advanced DFT methodologies for complex SoCs and ASICs.

Key Responsibilities

• Develop and implement DFT architectures for SoC/ASIC designs.
• Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan.
• Work on tool flows for Synopsys/Mentor/Cadence DFT tools.
• Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features.
• Debug and resolve issues during synthesis, simulation, and silicon bring-up.
• Deliver high-quality test coverage while optimizing for area, power, and performance impact.
• Support ATE patterns generation and silicon validation.

Required Qualifications

• Strong knowledge of DFT methodologies (Scan, ATPG, BIST, Boundary Scan, JTAG, compression techniques).
• Hands-on experience with industry-standard DFT EDA tools (Synopsys DFTMAX/TetraMAX, Cadence Modus, Mentor Tessent).
• Good understanding of RTL design, logic synthesis, timing, and verification.
• Solid debugging and problem-solving skills across pre-silicon and post-silicon phases.
• Experience in handling complex SoC/ASIC designs with multi-million gates.
• Scripting skills (Perl, Python, Tcl, Shell) for automation.
• Excellent communication and teamwork skills.

Nice-to-Have

• Bachelor's/Master's degree in Electronics/Electrical/Computer Engineering or related field.
• Exposure to low-power DFT techniques and advanced nodes (7nm/5nm/3nm).
• Experience in ATE test bring-up and production test support.

Compensation and Benefits

• Competitive salary and performance-based bonuses.
• Health, dental, and vision insurance.
• Retirement plan with employer matching.
• Paid time off and holiday leave.
• Ongoing training and professional development opportunities.

Additional Information

This position is part of the engineering department, and the successful candidate will report to the DFT Engineering Manager.