Design Engineering Architect

Cadence Design Systems; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Cadence Design Systems in Bengaluru is seeking a Lead Analog Design Engineer to drive CMOS analog/mixed-signal IC design for high-speed SERDES applications. You will develop blocks from concept through verification and work with layout teams to ensure conformance to customer specs.

The role requires deep CMOS experience, proficiency with CAD tools, and collaboration with global teams across time zones. Strong problem-solving and communication skills are essential.

Qualifications

• Minimum 8 years CMOS design experience, preferably in CMOS SERDES or high-speed I/O.
• Good understanding of jitter and signal equalization techniques.
• Experience with SERDES blocks: Driver, Receiver, Serializer, Deserializer, PLL, high-speed clock distribution.
• Proficient in CAD tools for circuit simulation, layout and physical verification.
• Excellent problem-solving, communication skills, and teamwork.

Responsibilities

• Design High Speed D2D and SERDES products at industry data rates on leading-edge nodes.
• Develop analog/mixed-signal IC blocks from concept to verification against specs.
• Collaborate with Layout Engineers to design IC blocks and PMA sections.
• Assist Technical Leads on circuit design and SERDES architectures.
• Coordinate with global teams across US time zones.

Skills

CMOS design

SERDES/high-speed I/O

Jitter/signal integrity

Team collaboration

Problem solving

Education

BEng/MEng/PhD or equivalent

Tools

Cadence

CAD tools for simulation

layout/verification tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.

Job Responsibilities:

• Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Layout Design Engineers to design IC circuit blocks and PMA sections
• Work with Technical Team Leads in the areas of circuit design and SERDES architectures
• Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications:

• BEng, MEng, PhD or equivalent.
• Candidate’s background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design
• Should have a good understanding of jitter and signal equalization techniques
• Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification

Additional Skills/Preferences:

• Cadence tool experience is desirable and design experience at >10Gbps and in <16nm technologies
• Lab test experience as part of silicon evaluation is advantageous

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