Lead Analog Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks a senior Analog/Mixed-Signal IC Designer to architect and deliver high-performance IPs for advanced-node SoCs. You will drive transistor-level design, verification, and silicon bring-up across PVT corners, collaborating with multiple teams to ensure first-pass silicon success.

The candidate will have 6–12 years of hands-on experience in Analog/Mixed-Signal IC Design, with expertise in PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, and

Qualifications

• 6–12 years of hands-on Analog/Mixed-Signal IC Design experience.
• Experience with transistor-level design, verification, and layout-aware optimization.
• Exposure to advanced nodes (16nm/7nm/5nm/3nm) is a plus.

Responsibilities

• Lead design and development of Analog IPs including PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, high-speed IOs and Clocking Circuits.
• Perform transistor-level circuit design, simulation, optimization and verification across PVT and Monte Carlo corners.
• Drive schematic design, pre/post-layout simulations, parasitic-aware optimization and silicon correlation.
• Collaborate with Analog Layout, Physical Design, Reliability, DFT, and Product Engineering teams through tapeout.
• Optimize designs for performance, power, area, noise, mismatch, yield and reliability.
• Mentor engineers and drive analog design methodology and design reviews.

Skills

Analog/Mixed-Signal IC Design

PLL

LDO

Bandgap

ADC

DAC

SerDes

DDR PHY

PMIC

High-Speed IOs

Clocking Circuits

Tools

Cadence Virtuoso

Spectre

ADE XL/Assembler

Job description

Lead the design and development of high-performance Analog/Mixed-Signal IPs for advanced-node SoCs. Drive analog architecture, circuit design, verification, and silicon bring-up for first-pass silicon success.

What You’ll Do

• Design and deliver Analog IPs including PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, High-Speed IOs, and Clocking Circuits.
• Perform transistor-level circuit design, simulation, optimization, and design verification across PVT and Monte Carlo corners.
• Drive schematic design, pre/post-layout simulations, parasitic-aware optimization, and silicon correlation.
• Collaborate with Analog Layout, Physical Design, Reliability, DFT, and Product Engineering teams through tapeout.
• Optimize designs for performance, power, area, noise, mismatch, yield, and reliability.
• Mentor engineers and drive analog design methodology and design reviews.

What You Bring

• 6–12 years of hands-on experience in Analog/Mixed-Signal IC Design.
• Strong expertise in one or more domains: PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, Data Converters, High-Speed Interfaces.
• Expertise in CMOS analog design, feedback systems, biasing, amplifiers, comparators, oscillators, and voltage references.
• Hands-on experience with Cadence Virtuoso, Spectre, ADE XL/Assembler, and analog simulation methodologies.
• Strong understanding of device physics, noise, mismatch, stability, compensation, PVT, Monte Carlo, ESD, and reliability.
• Experience with advanced technology nodes (16nm/7nm/5nm/3nm) is preferred.

Preferred

• Exposure to Low-Power Design, FinFET, and silicon bring-up/debug.
• Scripting experience in SKILL, Python, or Tcl is a plus.

We’re looking for engineers who can architect high-performance analog circuits, solve complex transistor-level design challenges, and deliver robust silicon for next-generation semiconductor products.