Lead Principal Analog design Engineer

Cadence; Hyderabad; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Cadence is seeking a Principal Analog Design Engineer in Hyderabad to lead the design and delivery of high-speed interface IPs with emphasis on D2D interconnects based on UCIe. You will own architecture through silicon bring-up, partnering with layout, verification, packaging, and system teams.

The role demands hands-on ownership, strong SI and packaging awareness, and collaboration across AMS verification, digital, and system groups to enable full-chip integration and validation.

Qualifications

• Bachelor’s or Master’s in Electrical/Electronics Engineering.
• 8+ years in analog/mixed-signal IC design.
• Knowledge of UCIe and chiplet architectures.
• Experience with high-speed interfaces (DDR, PCIe, SerDes).
• Experience with packaging effects on high-speed signaling.
• Schematic design, simulation, and debugging across PVT.

Responsibilities

• Own analog blocks for high-speed interfaces (clocking, TX/RX, termination, biasing).
• Drive architecture, feasibility analysis, and design trade-offs considering SI, power, and packaging parasitics.
• Perform schematic design, simulation, and optimization across PVT corners.
• Collaborate with advanced package teams (2.5D/3D) to co-optimise circuit and package design.
• Support layout reviews, parasitic extraction, and post-layout sign-off for high-speed performance.
• Collaborate with AMS verification, digital, and system teams for full-chip integration and validation.
• Participate in silicon bring-up, debug, and characterization, including correlation with simulation results.
• Contribute to design methodology and best practices for high-speed analog and D2D designs.

Skills

UCIe PHY design

DDR/PCIe/SerDes

Analog/Mixed-signal IC design

Signal integrity & timing

Mentor engineers

D2D chiplet architectures

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering

Tools

EDA tools

AMS verification tools

Post-silicon debug tools

Job description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other - every day.

About the Role

We are looking for an experienced Principal Analog Design Engineer to drive the design and delivery of high-speed interface IPs, with a strong emphasis on Die-to-Die (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires hands-on ownership from architecture through silicon bring-up, working closely with layout, verification, package, and system teams.

Responsibilities

• Own analog blocks for high-speed interfaces such as clocking, TX/RX front-ends, termination schemes, biasing, and equalization support circuits.
• Drive architecture definition, feasibility analysis, and design trade-offs considering signal integrity, power, noise, and packaging parasitics.
• Perform schematic design, simulation, and optimization across PVT corners using industry-standard EDA tools.
• Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co-optimise circuit and package design.
• Support layout reviews, parasitic extraction analysis, and post-layout sign-off for high-speed performance.
• Collaborate with AMS verification, digital, and system teams to enable full-chip integration and validation.
• Participate in silicon bring-up, debug, and characterization, including correlation with simulation results.
• Contribute to design methodology, checklists, and best practices for high-speed analog and D2D designs.

Qualifications

• Bachelor’s or Master’s degree in Electrical / Electronics Engineering or related field.
• 8+ years of hands-on experience in analog / mixed-signal IC design.
• Strong experience with high-speed interface design (e.g., DDR, PCIe, SerDes, Die-to-Die links).
• Solid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architectures.
• Experience working with advanced packaging technologies and understanding package-induced effects on high-speed signaling.
• Proficiency in schematic-level design, simulation, and debug across PVT corners.
• Strong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking.

Required Skills

• Direct hands-on experience with UCIe PHY design or integration.
• Exposure to AMS verification flows and mixed-signal simulation environments.
• Experience with post-silicon debug and correlation.
• Knowledge of power integrity, thermal considerations, and package-aware design flows.
• Ability to mentor junior engineers and lead technical discussions.

Preferred Skills

• Robust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability targets.
• Smooth collaboration across design, verification, and packaging teams.
• Predictable execution aligned with project milestones and KPIs/ OKRs.
• Strong ownership mindset from architecture to silicon.