Analog & Mixed-Signal IC Design Lead Engineer

Phizenix; Bengaluru; On-site; INR 4,000,000 - 7,500,000; Full time

Job summary

Phizenix in Bengaluru seeks an Analog & Mixed‑Signal IC Design Lead to drive the definition, execution, and delivery of high‑speed interconnect silicon, with hands‑on expertise in SerDes front‑ends, >10Gbps links, and precision data converters.

You will lead a multi‑engineer team from architecture to tape‑out across 5–16 nm FinFET/SOI, coordinate external vendors, and ensure delivery against PPA targets with strong project planning.

Qualifications

• Ph.D. or MS with 6+ years in analog/mixed-signal IC design.
• Proven leadership of analog/mixed-signal teams with multiple tape-outs.
• Experience in 7–16 nm FinFET or SOI processes.
• Experience with external contractors and IP vendors.

Responsibilities

• Lead an analog/mixed-signal design team through architecture to tape-out.
• Plan execution across advanced CMOS nodes and manage schedules.
• Engage external design contractors and IP vendors.
• Design and verify SerDes front-ends, ADCs, DACs, and clock distribution.
• Drive pre-silicon simulations and post-silicon bring-up.

Skills

High-speed SerDes design

Analog/mixed-signal leadership

Tape-out execution

CMOS FinFET 5–16nm

Pre-silicon & post-silicon bring-up

External contractors management

Project planning & scheduling

Education

Ph.D. in Electrical Engineering

M.S. in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Ultrasim

Oscilloscopes

VNAs

BERT setups

Job description

Analog & Mixed-Signal IC Design Lead Engineer

Role Overview

We are seeking an Analog & Mixed-Signal IC Design Lead to drive the definition, execution, and delivery of next‑generation high‑speed interconnect silicon. This is a technical leadership role for an accomplished designer who pairs deep, hands‑on expertise in high‑speed wireline and mixed‑signal design—SerDes front‑ends, serial links beyond 10 Gbps, and precision data converters—with a proven track record of leading teams through multiple successful tape‑outs in advanced CMOS nodes, including managing external design contractors to scale execution.

Key Responsibilities

Technical Leadership & Execution

• Lead an analog/mixed‑signal design team across the full cycle—architecture, design, verification, tape‑out, and bring‑up—owning delivery for multiple concurrent tape‑outs.
• Plan execution across advanced CMOS nodes: block partitioning, schedules, resource allocation, and PPA targets.
• Engage and manage external design contractors and IP vendors—scoping, reviewing, and integrating outsourced blocks to spec and schedule.
• Enforce design‑review discipline and shared methodologies, and mentor the team as its primary technical escalation point.

Hands‑On Design

• Design and verify high‑speed analog/mixed‑signal circuits: SerDes front‑ends, serial links (>10 Gbps), ADCs, DACs, clock distribution, laser/modulator drivers, and TIAs.
• Architect wireline SerDes front‑ends, optical interconnect ICs, and multi‑Gbps signal chains from concept through tape‑out.
• Develop transistor‑level schematics and guide layout in advanced FinFET (7–16 nm) or SOI to meet PPA targets.
• Drive pre‑silicon simulation and post‑silicon bring‑up, closing specification gaps from measured silicon data.

Required Qualifications

Education & Experience

• Ph.D. in Electrical Engineering (or related) with 6+ years, OR M.S. with 8+ years of analog/mixed‑signal IC design experience.
• Proven experience leading analog/mixed‑signal teams to successful execution, with multiple tape‑outs delivered in advanced CMOS nodes.

Core Technical Skills

• High‑speed wireline link design: broadband front‑ends, wideband amplifiers, equalization (CTLE), line drivers, and SerDes front‑ends.
• Building serial links beyond 10 Gbps, with knowledge of protocols such as PCIe, UCIe, and Ethernet / SerDes (NRZ / PAM‑4).
• Laser/modulator drivers and TIAs for optical interconnect; high‑speed ADC/DAC (SAR, pipeline, flash, current‑steering) for DSP‑based links.
• Hands‑on design and multiple tape‑outs in advanced CMOS / FinFET (5–16 nm) and/or SOI.

Leadership & Program Skills

• Proven ability to lead a multi‑engineer team from architecture to silicon sign‑off, and to manage external contractors and IP vendors.
• Strong project‑planning, schedule‑management, and cross‑functional communication skills.

Preferred Qualifications

• Familiarity with wireline PHY architectures (56G / 112G PAM‑4 SerDes, NRZ) and die‑to‑die interconnect (UCIe).
• Optical module ICs (TOSA/ROSA driver ASICs, coherent DSP interfaces); full‑duplex, echo‑cancellation, or DSP‑based link architectures.
• Cadence Virtuoso, Spectre / APS / Ultrasim, and lab characterization (oscilloscopes, VNAs, BERT setups).