RTL Senior Design Architect

NXP Semiconductors; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

NXP Semiconductors in Hyderabad seeks an experienced Hardware Architect to own SOC architecture from concept to silicon, balancing performance, power and area for AI inference accelerators.

You will define interfaces, drive PPA trade-offs with RTL and physical design teams, and mentor co-design with software. Requires 10+ years in SOC design and hands-on Verilog/SystemVerilog.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in SOC design, SOC architecture, RTL design, micro-architecture.
• Strong understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures.
• Proven experience optimizing for performance, power, and area.
• Hands-on expertise in Verilog/SystemVerilog, C/C++, and scripting (Python/Tcl/Perl)

Responsibilities

• Define product feature and architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
• Collaborate with software teams to co-optimize hardware features for AI workloads.
• Collaborate with RTL designers to identify complex technical issues/risks; review RTL implementation with timing/power goals.
• Collaborate with Physical-design teams for Area/Floorplan refinement, Timing targets.
• Define and document interface specifications, control/status logic, and pipeline structures.
• Lead PPA analysis and trade-off discussions across RTL and architecture.
• Collaborate with software teams for AI workloads co-design and dataflow decisions.
• Incorporate quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions.
• Develop and maintain high-level architecture and performance models; use simulations to guide RTL improvements.
• Validate model predictions against RTL or emulation results and refine accordingly.
• Strong understanding of AI inference workloads and memory/bandwidth bottlenecks in edge deployments.

Skills

SOC design

Architecture

RTL design

Micro-architecture

Verilog/SystemVerilog

C/C++

Scripting (Python/Tcl/Perl)

AI accelerators familiarity

Dataflow/Performance modeling

Education

Bachelor’s/Master’s in Electrical or Computer Engineering

Tools

EDA tools

Job description

We are seeking an experienced Hardware Architect with strong expertise in SOC-architecture, Micro-architecture design, RTL coding and system-level performance/power analysis. The ideal candidate will have a track record of owning complex blocks or subsystems from concept through silicon, balancing performance, power, and area (PPA), and working closely with software, asic-design, asic-verification, asic-physicaldesign teams. it requires deep architectural insight and hands-on implementation understanding to help guide design trade-offs and drive the next generation of AI inference accelerators.

• Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
• Collaborate with various software teams to co-optimize hardware features for AI workloads.
• Collaborate with RTL designers to identify complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals
• Collaborate with Physical-design teams for Area/Floorplan refinement, Timing targets etc.
• Define and document interface specifications, control/status logic, and pipeline structures.
• Lead PPA analysis and trade-off discussions across RTL and architecture.

AI Workloads & HW-SW Co-Design

• Collaborate closely with various software to co-optimize hardware features for real-world AI inference workloads.
• Incorporate considerations such as, quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions.
• Guide hardware features that improve programmability, debuggability, and long-term software scalability.
• Develop and maintain high-level architecture and performance models.
• Use simulation and architectural models to guide RTL-level improvements.
• Validate model predictions against RTL or emulation results and refine accordingly.
• Strong understanding of AI inference workloads, dataflows, quantization, and memory/bandwidth bottlenecks in edge deployments

Job Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in SOC design, SOC architecture, RTL design, micro-architecture.
• Strong understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures.
• Proven experience optimizing for performance, power, and area.
• Hands-on expertise in Verilog/SystemVerilog, C/C++, and scripting (Python/Tcl/Perl)

Preferred Qualifications:

• Experience with AI accelerators, DSPs, or high-performance CPUs/GPUs.
• Familiarity with performance modeling frameworks (e.g., Python/C++ based).
• Exposure to EDA tools, power/performance analysis, and hardware-software co-design.
• Strong analytical skills and a collaborative mindset.