CPU DFT Manager

Intel; Bengaluru; Hybrid; INR 400,000 - 700,000; Full time

Job summary

Intel in Bengaluru is seeking an experienced DFT leader to guide a high‑performing team focused on X86 CPU DFT design and validation. You will develop execution plans for parallel projects and ensure timely, high‑quality delivery.

Responsibilities include implementing JTAG, Memory BIST and Memory Repair circuitry; driving DFT verification via RTL simulations and emulation; creating test plans for complex microarchitecture and collaborating with post‑silicon/manufacturing teams on ATE issues.

Qualifications

• 10+ years of experience in DFT domain at IP or SoC level.
• 5+ years of experience managing and leading teams.
• Strong knowledge and experience in Spyglass DFT.

Responsibilities

• Lead and guide a high‑performing DFT team focused on X86 CPU DFT design and validation.
• Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high‑quality delivery.
• Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation.
• Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides.
• Collaborate with post‑silicon/manufacturing teams on ATE, debugging and resolving issues.

Skills

DFT leadership

X86 CPU DFT

RTL verification

RTL coding

Shell scripting

JTAG

Memory BIST

Memory Repair

Post-silicon collaboration

Cross-site leadership

Tools

Spyglass DFT

Job description

Responsibilities

• Leadership and Management:
  • Manage and technically guide a high‑performing DFT team focused on X86 CPU DFT design and validation.
  • Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high‑quality delivery.
• DFT Design and Verification:
  • Implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry‑standard tools.
  • Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation.
  • Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides.
• Technical Problem Solving:
  • Debug failures to root cause and learn architecture/microarchitecture deeply.
  • Collaborate with post‑silicon/manufacturing teams on ATE, debugging and resolving issues.
• Cross‑Functional Collaboration:
  • Work closely with global stakeholders to address DFT challenges and improve product quality.
  • Ensure alignment of timelines and deliverables across sites.

Qualifications

• 10+ years of experience in DFT domain at IP or SoC level.
• 5+ years of experience managing and leading teams.
• Strong knowledge and experience in Spyglass DFT.
• Hands‑on skills in implementing JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry.
• Expertise in DFT Design and verification using RTL simulations and emulation.
• Good understanding of timing constraints and DFT mode timing analysis.
• Proficiency in RTL coding and shell scripting.
• Experience working with post‑silicon/manufacturing teams on ATE, including debugging and issue resolution.
• Experience with X86 CPU architecture and microarchitecture.
• Familiarity with advanced process nodes and hierarchical DFT strategies.
• Strong communication and leadership skills for cross‑site collaboration.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Business Group

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.