CPU Design Verification Engineer

Altera; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

Altera in Bengaluru, Karnataka, India is seeking an experienced CPU Design Verification Engineer to validate the RISC-V processor family. You will collaborate with architects, RTL designers, and system teams to ensure functional correctness and performance targets are met across pre-silicon runs and system-level simulations.

You will develop scalable UVM-based testbenches, drive functional coverage, identify gaps, and implement closure plans.

Qualifications

• Bachelor’s or Master’s degree in Electronics or Computer Engineering.
• 8+ years of ASIC/FPGA design verification experience.
• HDL knowledge: Verilog or VHDL; SystemVerilog expertise.
• Hands-on with UVM-based testbenches and verification components.
• Experience with RISC-V instruction set architecture.

Responsibilities

• Develop and execute verification plans for CPU logic.
• Create scalable UVM testbenches and coverage models.
• Perform functional coverage analysis and close gaps.
• Run complex system-level simulations and debug pre-silicon issues.
• Automate workflows with Python, Perl, or Tcl.

Skills

UVM-based verification

RISC-V

CDV/ABV

Python

SystemVerilog

Education

Bachelor’s or Master’s degree in Electronics Engineering or Computer Engineering

Tools

Verilog

VHDL

SystemVerilog

Synopsys VCS

Cadence Xcelium

Mentor Questa

AMBA (AXI/ACE/CHI)

Python

Job description

Job Description:

As a CPU Design Verification Engineer, you’ll play a pivotal role in ensuring the functional correctness and performance of Altera’s RISC-V processor family. Working alongside world-class CPU architects, RTL designers, and system design teams, you’ll help validate designs that meet rigorous functional, performance goals. This is your opportunity to tackle complex technical challenges while contributing to products that shape the computing landscape.

Key Responsibilities

• Develop and execute sophisticated verification plans to validate CPU logic against architectural and microarchitectural specifications

• Create scalable, reusable verification environments using UVM-based testbenches and advanced functional coverage models

• Perform in-depth functional coverage analysis, identify critical verification gaps, and implement strategic closure plans

• Execute complex system-level simulations to validate functionality

• Debug and perform root-cause analysis of issues in pre-silicon environments, implementing robust corrective measures

• Develop automation scripts and tools using Python, Perl, C++, or similar languages to optimize verification workflows

• Partner closely with CPU architects and RTL developers to verify complex architectural features

• Maintain and enhance verification infrastructure, methodologies, and automation flows to maximize team productivity

• Document comprehensive verification strategies and lead technical reviews with cross-functional stakeholders

• Contribute to CPU architecture and microarchitecture feature definition to achieve optimal functional and performance targets

Qualifications:

• Bachelor’s or Master’s degree in Electronics Engineering, Computer Engineering.

• 8+ years of experience in ASIC or FPGA design verification.

• Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as System Verilog.

• Strong hands-on experience in developing UVM-based testbenches and verification components.

• Experience with RISC-V instruction set architecture.

• Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).

• Familiarity withindustry-standard protocols such as AMBA (AXI, ACE, CHI, APB)

• Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.

• Excellent analytical, problem-solving, and debugging skills.

• Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Bengaluru, Karnataka, India

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.