Principal Verification Engineer

Altera; Bengaluru; Remote; INR 1,500,000 - 2,500,000; Full time

Job summary

A technology company is seeking a talented Principal Verification Engineer in Bengaluru, Karnataka. The ideal candidate will have over 10 years of experience in ASIC or FPGA design verification, with strong skills in SystemVerilog and UVM. Responsibilities include developing verification environments, creating test cases, and collaborating with design engineers. This role encourages problem-solving and teamwork within a collaborative environment. The company offers a regular position with options for remote work.

Qualifications

• 10+ years of experience in ASIC or FPGA design verification.
• Strong hands-on experience in developing UVM-based testbenches.
• Familiarity with industry-standard protocols such as AMBA, PCIe, or Ethernet.

Responsibilities

• Collaborate with engineers to define verification strategies.
• Develop reusable verification environments using SystemVerilog.
• Create directed and random test cases to uncover bugs.
• Execute simulation regressions and analyze test failures.

Skills

SystemVerilog

UVM (Universal Verification Methodology)

Verilog or VHDL

Python

Problem-solving

Collaboration

Communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Simulation tools

Debug tools

Job description

Overview

Altera is looking for a talented and driven Principal Verification Engineer to design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
• Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
• Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Qualifications

• Bachelor\'s or master\'s degree in electrical engineering, computer engineering, or a related field.
• 10+ years of experience in ASIC or FPGA design verification.
• Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
• Strong hands-on experience in developing UVM-based testbenches and verification components.
• Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
• Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
• Experience with simulation and debug tools.
• Strong scripting skills in Python, Perl, or TCL or automation and data analysis.
• Excellent analytical, problem-solving, and debugging skills.
• Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.

Job Type

Regular

Shift

Shift 1 (India)

Location

Primary Location: New Delhi, India (Remote)

Additional Locations: Bengaluru, Karnataka, India

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.