CAD Layout Design Engineer

NVIDIA; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Benefits offered by this job

Competitive salaries

Generous benefits package

Job summary

A leading technology company is looking for a CAD Layout Design Engineer to join their innovative Layout Methodology team. This role involves accelerating layout creation and improving productivity for digital IPs like SRAM and analog blocks. Candidates should have a BE/M-Tech in Electrical & Electronics, 5+ years of experience, and expertise in advanced technology nodes. Proficiency in Cadence SKILL, Python, Perl, and Shell scripting is essential. Join a company known for competitive salaries and excellent benefits.

Qualifications

• 5+ years of experience in layout design.
• Experience with SRAM/Analog layout design.
• Knowledge of advanced technology nodes like 5,3 or 2 nanometers.

Responsibilities

• Enable layout work in new technology via digital IP creation.
• Conduct in-depth studies of new technology for layout.
• Coordinate analysis of new technology for layout guidelines.

Skills

Project cycle experience

Cadence SKILL language proficiency

Scripting in Python

Scripting in Perl

Scripting in Shell

Good social skills

Excellent presentation skills

Ability to communicate new ideas

Education

BE/M-Tech in Electrical & Electronics or equivalent

Job description

CAD Layout Design Engineer

We are looking for a CAD Layout Design Engineer to join the groundbreaking Layout Methodology team, chartered to accelerate layout creation, improve productivity, and shorten time to market for Nvidia digital IP such as SRAM layouts and analog blocks.

What You’ll Be Doing

• You will be part of the groundbreaking "Layout Methodology" team with a charter to speed up layout creation, productivity and improve time to market of Nvidia digital IP like SRAM layouts and other custom Analog layout blocks.
• Be the first to conduct an in-depth study of new technology and enable the rest of the design teams to seamlessly start off on new/advanced layout technology.
• Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
• Coordinate analysis of new technology and translating into guidelines for EMIR, DFM, SRAM layout guidelines etc.
• Investigate next generation tools for layout creation.
• Investigate the applications of Machine Learning / Deep Learning / LLM techniques for layout creation.

What We Need To See

• BE/M-Tech in Electrical & Electronics or equivalent experience.
• 5+ years of experience.
• Proven project cycle and tape out experience in SRAM/Analog layout design.
• Experience in advanced technology nodes like 5,3 or 2 nanometers is a must.
• Solid proficiency / expertise in the Cadence SKILL language is a requirement for this job.
• Experience with PCELL development is a big requirement.
• Solid scripting skills in Python, Perl, Shell is a requirement.
• Good social skills and be an excellent teammate.
• Excellent presentation and influencing skills and ability to communicate new ideas/tools to other groups.

We are an equal opportunity employer and value diversity at our company. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers.