ASIC Verification Engineer

4323 LSI India Research & Development Private Limited; Pune District; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Broadcom, Inc. in Pune district, India, is seeking an experienced Verification Engineer to lead the development of test plans and verification environments for Block/Core/SOC platforms.

The role focuses on writing functional coverage, building scalable test benches, and debugging RTL/Gate level regressions. Ideal candidates have 8+ years in SystemVerilog with UVM-like methodologies, strong OO programming, and familiarity with PCIe/SAS/SATA and AMBA protocols.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering or related field.
• 8+ years of relevant experience.
• Proficiency in SystemVerilog and verification methodologies like UVM/VMM/OVM.
• Knowledge of Host interface protocols such as PCIe, SAS, SATA is desired.
• Familiarity with AMBA AXI/AHB/APB protocols.
• Experience writing Functional Coverage and pseudo random tests.
• Ability to work independently on IP/Subsystem/SoC projects.

Responsibilities

• Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features
• Develop verification environments using System Verilog and UVM Architect and develop scalable and re-usable test benches, using the framework of the verification methodology
• Develop BFMs / Checkers / monitors / Scoreboards
• Build pseudo-random tests to verify and get full Functional coverage
• Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps
• Document verification strategy including Test plans, Testbench, Random tests, etc.

Skills

SystemVerilog

Object-Oriented Programming

Functional coverage

Education

Electrical Engineering degree (Bachelor/Master)

Tools

UVM/VMM/OVM

Job description

Job Description

• Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features
• Develop verification environments using System Verilog and UVM Architect and develop scalable and re-usable test benches, using the framework of the verification methodology
• Develop BFMs / Checkers / monitors / Scoreboards
• Build pseudo-random tests to verify and get full Functional coverage
• Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps
• Document verification strategy including Test plans, Testbench, Random tests, etc.

Requirements

• Bachelor’s or Master’s degree in electrical engineering or related degree with 8+ years relevant experience
• Proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM
• Good command of Object-Oriented Programming principles
• Knowledge of Host interface protocols such as PCIe, SAS, SATA is desired
• Knowledge of AMBA AXI/AHB/APB protocols
• Experience writing Functional Coverage, pseudo random tests
• Flexible to work in any IP/Subsystem/SoC projects
• Capability to work independently and deliver

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.