Associate III - VLSI STA SG

UST; Bengaluru; On-site; INR 700,000 - 1,100,000; Full time

Job summary

UST Bengaluru is seeking an STA engineer to run timing analysis tools, debug issues, and drive ECO generation across MCMM. You will analyze ECO quality and communicate findings to the design team during fixes. Hands-on with ICC2 and FC is desirable, along with scripting in Tcl, Perl, and Python.

Ideal candidates hold a B.Tech/B.E or M.Tech/M.E with 2–4 years of experience and a solid understanding of design metrics and .lib/.db generation and analysis.

Qualifications

• 2–4 years of experience as a STA engineer.
• Experience with Synopsys STA tools preferred.
• Knowledge of lib/.db fields and .lib generation.
• Scripting skills in Tcl, Perl, Python.

Responsibilities

• Run STA tools and independently debug STA issues.
• Generate ECO across MCMM and analyze ECO quality.
• Provide feedback to design team during fixes.
• Understand different design metrics and implications.

Skills

Static Timing Analysis

Tcl

Physical Design

Perl

Education

B.Tech/B.E/M.Tech/M.E

Tools

ICC2

FC

Job description

Role Description

Job Description: Title: STA engineer required Role and Responsibilities: Candidate should be able to run STA tools ( Synopsys tools preferred) independently, understand STA methodology and debug STA issues. Candidate is also expected to generate ECO across MCMM, analyse ECO quality and give feedback to design team during fix . Hands on knowledge on ICC2, FC is desirable. Candidate should also be able to understand different design metrics . Should have adequate knowledge on .lib generation and analysis of different fields inside .lib/.db . He/She should have good scripting knowledge as well (Tcl, perl , python etc ) Skill Requirements: STA Good to have: PD, circuit simulation , scripting knowledge Experience: 2-4 Years Qualifications: B.Tech/B.E/M.Tech/M.E

Skills

• Static Timing Analysis
• Tcl
• Physical Design
• Perl