Senior Engineer - STA

Quest Global; Hyderabad; On-site; INR 4,500,000 - 6,000,000; Full time

Job summary

Quest Global Hyderabad is seeking an experienced Physical Design Lead to own the end-to-end PD flow for complex SoC/ASICs. You will drive floorplanning, placement, routing, CTS, and signoff, ensuring timing closure across PVT/MMMC conditions.

Collaborate with RTL, DFT, and verification teams, mentoring a small team and enhancing flows with scripting. Knowledge of low-power techniques and advanced nodes is preferred.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics or related field.
• 7–11 years of relevant Physical Design experience on large SoC/ASIC projects.
• Proven tapeout track record in advanced technology nodes.

Responsibilities

• Own end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs.
• Lead floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas).
• Drive timing closure across PVT and MMMC analyses.
• Work on power planning and optimization (IR drop, EM, low-power design).
• Mentor juniors and drive flow automation and scripting.

Skills

Physical Design Tools

STA & Power optimization

Perl/Tcl/Shell

Low Power Techniques

Signoff & DRC/LVS

Education

BE/B.Tech/M.E/M.Tech in Electronics

Tools

Cadence Innovus

Cadence Voltus

Cadence Tempus

Cadence LEC

Synopsys PrimeTime

Synopsys StarRC

Calibre

Job description

Job Requirements

Roles & Responsibilities

• Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs.
• Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.).
• Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis.
• Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies).
• Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure.
• Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively.
• Experience in synthesis and formal equivalence checking (LEC) to ensure design quality.
• Familiarity with signoff methodologies and tapeout process.
• Mentor and guide junior engineers within the team, review their work, and drive best practices.
• Contribute to methodology improvements, flow automation, and scripting.

Key Skills

• Strong expertise in Physical Design EDA tools: Cadence (Innovus, Voltus, Tempus, LEC) or Synopsys (PrimeTime, StarRC)
• Hands-on with STA, Power, and Area optimization techniques.
• Proficiency in scripting (Perl/Tcl/Shell) for automation and flow enhancements.
• Experience with low power design techniques (UPF/CPF), multi-voltage domains, and advanced nodes (3nm/5nm/22nm/28nm as applicable).
• Solid understanding of physical verification and signoff (Calibre or equivalent).

Desired Profile

• B.E./B.Tech/M.E./M.Tech in Electronics, or related field.
• 7-11 years of relevant experience in Physical Design on large SoC/ASIC projects.
• Proven track record of successful tapeouts in advanced technology nodes.
• Good problem-solving skills and ability to work independently and as part of a team.
• Able to handle a small team of 4 members along with hands on
• Excellent communication and documentation skills.

Work Experience

• Strong expertise in Physical Design EDA tools: Cadence (Innovus, Voltus, Tempus, LEC) or Synopsys (PrimeTime, StarRC)
• Hands-on with STA, Power, and Area optimization techniques.
• Proficiency in scripting (Perl/Tcl/Shell) for automation and flow enhancements.
• Experience with low power design techniques (UPF/CPF), multi-voltage domains, and advanced nodes (3nm/5nm/22nm/28nm as applicable).
• Solid understanding of physical verification and signoff (Calibre or equivalent).