ASIC Verification Engineer

Hewlett Packard Enterprise Development LP; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a talented ASIC Verification Engineer located in Bengaluru, India. In this role, you will architect and develop verification environments, define and deliver test suites, and ensure verification of large ASIC blocks. You will work closely with design and software teams to resolve issues.

The ideal candidate has a MSEE or BSEE degree and at least 3 years of experience in ASIC verification, particularly using SystemVerilog and UVM methodologies.

Qualifications

• 3+ years of experience in ASIC Verification using SystemVerilog.
• Strong knowledge of constrained-random verification techniques.
• Experience with verification methodologies like OVM/VMM/UVM.

Responsibilities

• Architect and develop block level verification environments using System Verilog.
• Define and deliver verification suites/tests for ASICs.
• Verify large ASIC blocks independently for tape-out.

Skills

ASIC Verification using SystemVerilog

Experience in constrained-random verification

Verification methodology like OVM/VMM/UVM

Perl/Tcl scripting

Experience verifying networking protocols such as Ethernet

Problem solving and ASIC debugging skills

Education

MSEE or BSEE

Tools

VCS/Xcelium

Job description

Role & responsibilities

What you'll do:

• You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
• Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)
• Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/Xcelium) to perform this activity. (25%)
• Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
• Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%)

What you need to bring:

• ASIC Verification using SystemVerilog
• Experience in constrained-random verification is a strong plus
• Experience with verification methodology like OVM/VMM/UVM
• Perl/Tcl scripting is strongly preferred
• Experience verifying networking protocols such as Ethernet is desirable
• Strong problem solving and ASIC debugging skills
• MSEE or BSEE is required with 3 plus years of experience.