Verification Engineer

Indian Institute of Technology Delhi (IIT Delhi); Hyderabad; On-site; INR 1,000,000 - 2,000,000; Full time

Benefits offered by this job

Opportunity to work on cutting‑edge semiconductor projects

Collaborative and innovative work environment

Professional growth and leadership opportunities

Job summary

Indian Institute of Technology Delhi (IIT Delhi) is looking for a Senior Verification Engineer to join their semiconductor team. The role involves leading verification for ASIC designs, enhancing methodologies, and mentoring team members.

The ideal candidate will have a BS/MS in Electrical/Computer Engineering and 2+ years of ASIC verification experience. Strong skills in SystemVerilog, UVM, and industry tools like VCS are essential for success in this position.

Qualifications

• 2+ years of hands‑on ASIC verification experience.
• Strong proficiency with industry tools like VCS, Xcelium, and QuestaSim.
• Advanced debugging and problem‑solving capabilities.

Responsibilities

• Design and implement advanced System Verilog/UVM verification infrastructures.
• Lead verification planning and execution for complex ASIC projects.
• Develop comprehensive test strategies ensuring thorough design validation.
• Drive debug resolution through collaboration with cross-functional teams.

Skills

Expert-level SystemVerilog

UVM

Object-oriented programming

Industry tools (VCS, Xcelium, QuestaSim)

Debugging and problem-solving

Excellent communication

Python/Perl scripting

Education

BS/MS in Electrical/Computer Engineering

Job description

Job Title: Senior Verification Engineer (hardware)

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects.

About the Role

You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs.

What You'll Do

• Design and implement advanced System Verilog/UVM verification infrastructures
• Lead verification planning and execution for complex ASIC projects
• Develop comprehensive test strategies ensuring thorough design validation
• Drive debug resolution through collaboration with cross-functional teams
• Mentor and provide technical guidance to verification team members
• Enhance and optimize verification methodologies
• Own end-to-end SOC verification environments

Required Skills & Experience

• BS/MS in Electrical/Computer Engineering
• 2+ years of hands‑on ASIC verification experience
• Expert‑level SystemVerilog, UVM, and object‑oriented programming skills
• Strong proficiency with industry tools like VCS, Xcelium, QuestaSim
• Advanced debugging and problem‑solving capabilities
• Excellent communication and collaboration abilities
• CLP and GLS
• Python/Perl scripting expertise

Nice to Have

• Experience with PCIe, DDR, USB, C2C
• Knowledge of on‑chip interconnects and processor subsystems
• Background in formal verification methods
• Prior experience on Emulators

What We Offer

• Opportunity to work on cutting‑edge semiconductor projects
• Collaborative and innovative work environment
• Professional growth and leadership opportunities