Asic Verification Engineer

ACL Digital; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

ACL Digital in Bangalore invites an experienced PCIe Verification Engineer to lead pre-silicon verification for next-generation ASICs using PCIe Gen6/Gen7. You will define verification strategies and build robust UVM environments to ensure first-pass silicon success.

You'll architect constrained-random testbenches, author plans and coverage models, and verify full-chip blocks while debugging complex issues with RTL teams.

Qualifications

• Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering or related field.
• 7-8+ years hands-on ASIC/SoC pre-silicon verification experience.
• Deep architectural and protocol-level understanding of PCIe Gen6 and Gen7.
• Strong mastery of SystemVerilog and UVM.
• Experience building UVM testbenches, writing assertions, functional coverage, and test cases.
• Proficiency with industry-standard EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Scripting ability in Python, Perl, or Shell to automate flows.

Responsibilities

• Architect, develop, and maintain advanced constrained-random verification environments using SystemVerilog and UVM.
• Author verification plans, test scenarios, and coverage models based on PCIe Gen6/Gen7 specs.
• Execute block-level, sub-system, and full-chip verification for protocol compliance.
• Debug complex designs and testbenches with RTL engineers.
• Integrate and verify PCIe VIPs (Verification IP) including link training and data routing.
• Drive closure of functional and code coverage metrics to milestones.
• Mentor junior engineers and collaborate with global teams.

Skills

SystemVerilog

UVM

Constrained-random verification

Assertions (SVA)

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering

Tools

VCS

Xcelium

Questa

Job description

POSITION OVERVIEW

• Location: Bangalore, India
• Notice Period: 0 to 30 days (Immediate joiners preferred)
• Experience Required: 7 to 8+ years

JOB DESCRIPTION: PCIe VERIFICATION ENGINEER

Position Summary

We are seeking a highly experienced and technically sound PCIe Verification Engineer to join our core silicon engineering team. In this role, you will lead and execute the pre-silicon verification of next‑generation, high-performance ASICs utilizing PCIe Gen6 and Gen7 protocols. You will be responsible for defining verification strategies, building robust UVM environments, and ensuring first‑pass silicon success for cutting‑edge networking and computing hardware.

Key Responsibilities

• Architect, develop, and maintain advanced constrained‑random verification environments from scratch using SystemVerilog and UVM methodologies.
• Author comprehensive verification plans, test scenarios, and functional coverage models based on PCIe Gen6/Gen7 architectural specifications.
• Execute block‑level, sub‑system, and full‑chip SoC verification to ensure complete protocol compliance and functionality.
• Debug complex hardware designs, testbench components, and protocol violations alongside RTL designers and architects.
• Integrate and verify third‑party PCIe VIPs (Verification IP), ensuring proper hook‑up and configuration for high‑speed link training, physical layer behaviors, and data routing.
• Drive closure of functional and code coverage metrics, achieving 100% targeted milestones.
• Mentor junior engineers and collaborate effectively across global design and verification teams to accelerate time‑to‑market.

Required Technical Skills & Qualifications

• Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, Computer Engineering, or a related field.
• Experience: Minimum 7 to 8 years of dedicated hands‑on experience in ASIC/SoC Pre‑Silicon Verification.
• Protocol Expertise: Deep architectural and protocol‑level understanding of PCIe Gen6 and/or Gen7 (including flit‑based architectures, PAM4 signaling considerations at the protocol level, RAS features, virtualization, and low‑power states).
• Methodologies: Strong mastery of SystemVerilog and UVM (Universal Verification Methodology).
• Verification Infrastructure: Proven track record of building UVM testbenches, writing assertions (SVA), implementing functional coverage, and test case development.
• Tools: Proficiency with industry‑standard EDA tools from Synopsys (VCS), Cadence (Xcelium), or Siemens/Mentor Graphics (Questa).
• Scripting: Good command over scripting languages like Python, Perl, or Shell to automate verification flows.