Silicon Design For Test Engineer, Google Cloud

Google Inc.; Bengaluru; On-site; INR 1,000,000 - 1,600,000; Full time

Job summary

Google Inc. is looking for a Silicon Design For Test Engineer to develop custom silicon solutions for Google Cloud. The successful candidate will implement DFT logic and validate test patterns to enhance the efficiency and performance of Google services.

This role involves collaboration in a cutting-edge environment focusing on DFT implementations, low-level circuit design, and the reliability of silicon in Google’s data centers. Candidates should have a Bachelor's in Electrical Engineering and a solid understanding of DFT methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 2 years of experience in DFT methodologies and verification.
• Experience with scan insertion and ATPG.

Responsibilities

• Implement DFT Register-Transfer Level (RTL) logic.
• Generate and validate ATPG test patterns.
• Assist in post-silicon testing.

Skills

DFT methodologies

Gate level simulations

Python scripting

SoC designs

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in relevant field

Tools

Python

DFT tools

Job description

Silicon Design For Test Engineer, Google Cloud

Apply

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
• Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

Experience in SoC designs and integration flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• 1 year of experience with development projects in Very-Large-Scale Integration (VLSI).
• Experience scripting in Python or Perl or other related language.
  
• Experience or understanding of RTL design, SoC architecture, verification.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will help create the custom hardware, software, and networking technologies that power all of Google's services. You will focus on DFT implementation, generating test patterns, and validating them for post-silicon testing. You will own the entire process, from low-level circuit design to high-volume manufacturing. You will ensure the reliability of the custom silicon inside our data centers, ultimately impacting millions of users worldwide.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Implement DFT Register-Transfer Level (RTL) logic and validate the same. Generate and validate Automatic Test Pattern Generation (ATPG) test patterns for various SoC blocks under executive guidance.
• Implement and verify basic DFT logic like scan, MBIST, and boundary scan architectures.
• Perform gate-level simulations to verify the timing and functionality of specific test modes.
• Assist the team in post-silicon testing and debugging failure logs from Automated Test Equipment (ATE) data.
• Maintain and run automation scripts in Python or Tcl for standard DFT workflows.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.