ASIC RTL Design Engineer

Weekday AI (YC W21); Hyderabad; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Weekday AI in Hyderabad, India, seeks experienced ASIC RTL Design professionals from Senior Engineer through Architect levels to contribute to architecture and implementation of complex semiconductor products. You will work across RTL lifecycle—from understanding architectural specifications and developing microarchitecture to writing synthesizable RTL, supporting verification, and resolving design issues.

Depending on experience, you may own design blocks, provide technical leadership, and

Qualifications

• 6+ years of hands-on experience in ASIC RTL design or digital hardware development.
• Strong understanding of digital design fundamentals, RTL coding, and ASIC design methodologies.
• Proven experience developing synthesizable RTL for complex digital systems.
• Strong proficiency in Verilog/SystemVerilog and RTL design practices.

Responsibilities

• Develop high-quality, synthesizable RTL designs based on architectural specifications.
• Translate system requirements into digital hardware implementations.
• Design and implement complex digital logic blocks for ASIC products.
• Participate in microarchitecture definition and design reviews.
• Develop clean, reusable RTL using industry-standard methodologies.
• Collaborate with verification teams to define design requirements and resolve issues.
• Debug RTL and simulation issues and work with verification to identify root causes.
• Support synthesis, timing analysis, linting, CDC, and other design-quality activities.
• Analyze and optimize designs for performance, power, area, and reliability.

Skills

RTL design

Digital logic

ASIC development

Verilog/SystemVerilog

Architectural leadership

Mentoring

Design reviews

Debugging RTL

Job description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟯𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟯𝟬-𝟱𝟬 𝗟𝗣𝗔)

Experience: 6+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

We are looking for experienced ASIC RTL Design professionals to join the semiconductor engineering team at Senior Engineer through Architect levels. This role is suited for highly skilled engineers who have strong expertise in RTL design, digital logic, and ASIC development and are looking to contribute to the architecture and implementation of complex semiconductor products.

You will be involved across key stages of the RTL design lifecycle, from understanding architectural specifications and developing microarchitecture to writing synthesizable RTL, supporting verification, and resolving design issues. Depending on your experience level, you may also take ownership of design blocks, provide technical leadership, and contribute to architectural decisions.

Key Responsibilities

• Develop high-quality, synthesizable RTL designs based on architectural and microarchitectural specifications
• Translate system requirements into efficient digital hardware implementations
• Design and implement complex digital logic blocks for ASIC products
• Participate in microarchitecture definition, design reviews, and technical discussions
• Develop clean, reusable, and scalable RTL using industry-standard design methodologies
• Collaborate with verification teams to define design requirements and resolve functional issues
• Debug RTL and simulation issues and work closely with verification teams to identify root causes
• Support synthesis, timing analysis, linting, CDC, and other design-quality activities
• Analyze and optimize designs for performance, power, area, and reliability
• Work closely with physical design and implementation teams to address design constraints and integration challenges
• Review specifications, RTL, design documentation, and technical deliverables for quality and completeness
• Contribute to improving RTL design methodologies, coding standards, and development processes
• For senior and architect-level roles, provide technical leadership, mentor engineers, and drive complex design initiatives
• Participate in cross-functional technical reviews and contribute to architectural decisions

What Makes You a Great Fit

• 6+ years of hands-on experience in ASIC RTL design or digital hardware development
• Strong understanding of digital design fundamentals, RTL coding, and ASIC design methodologies
• Proven experience developing synthesizable RTL for complex digital systems
• Strong proficiency in Verilog/SystemVerilog and RTL design practices
• Experience with simulation, debugging, linting, CDC, synthesis, and other RTL design-quality processes
• Good understanding of ASIC development flows and collaboration across design, verification, and physical design teams
• Ability to analyze complex technical problems and develop efficient, reliable solutions
• Strong understanding of design trade-offs involving power, performance, and area (PPA)
• Excellent problem-solving, communication, and technical documentation skills
• Ability to work independently while collaborating effectively with cross-functional engineering teams
• Senior Engineer candidates should demonstrate ownership of complex RTL blocks, while Architect-level candidates should have strong experience in microarchitecture, technical leadership, and design strategy
• A strong passion for semiconductor technology and the ability to continuously learn and adapt to evolving ASIC design methodologies