Senior Methodology Engineer – Physical Design Automation

Deel; India; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Deel is seeking a Senior Methodology Engineer to drive automation for the RTL-to-Signoff Physical Design flow across complex SoC/ASIC projects. You will build scalable automation frameworks, improve design productivity, and enable high‑quality silicon delivery across advanced process technologies.

You will collaborate with Physical Design, STA, DFT, RTL, Library, and CAD teams to advance methodologies, implement data-driven improvements, and deliver robust quality metrics throughout the flow.

Qualifications

• Bachelor's or Master's in Electrical/Electronics or Computer Engineering.
• 4+ years in Physical Design, CAD Methodology, or Design Automation.
• Experience with RTL-to-GDSII Signoff flow and EDA workflows.
• Proficient in Python, Tcl, Perl, Shell, or C++ scripting.
• Hands-on with major EDA tools and flow customization.
• Familiarity with 7nm+ nodes and CAD infrastructure.
• Exposure to AI/ML or LLM-based automation in EDA is a plus.

Responsibilities

• Develop and maintain automation frameworks for RTL-to-Signoff flow.
• Build methodology solutions for synthesis, floorplanning, routing, and signoff.
• Create quality checks, validation, and reporting systems.
• Develop data pipelines for analysis and productivity gains.
• Collaborate with Physical Design and CAD teams to improve methods.
• Drive improvements in timing, power, area, and verification closure.
• Define best practices and signoff methodologies across projects.
• Support advanced-node challenges with automation and data-driven solutions.

Skills

Automation

Python

Tcl

C++

Shell

Perl

EDA tools

Data pipelines

Quality dashboards

Education

Bachelor's degree in Electrical/Electronics Engineering

Master's degree in related field

Tools

Design Compiler

Fusion Compiler

ICC2

PrimeTime

ICV

StarRC

Innovus

Tempus

Voltus

Pegasus

Calibre DRC/LVS/ERC

Python

Tcl

Job description

We are seeking a highly motivated Senior Methodology Engineer to drive the development of advanced Physical Design automation, methodologies, and quality systems for complex SoC and ASIC designs. The ideal candidate will combine strong expertise in the RTL-to-Signoff Physical Design flow with software development skills to build scalable automation frameworks, improve design productivity, and enable high-quality silicon delivery across advanced process technologies.

Key Responsibilities

• Develop and maintain automation frameworks supporting the complete RTL-to-Signoff Physical Design flow.
• Build methodology solutions for synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and signoff.
• Create quality checking, validation, and reporting systems for implementation and signoff metrics.
• Develop scalable tools, scripts, and data pipelines for design analysis, productivity enhancement, and methodology optimization.
• Collaborate with Physical Design, STA, DFT, RTL, Library, and CAD teams to improve implementation methodologies and design quality.
• Drive continuous improvements in timing, power, area, congestion, IR/EM, and physical verification closure.
• Define and maintain best practices, design guidelines, and signoff methodologies across multiple projects.
• Support advanced-node implementation challenges through innovative automation and data-driven solutions.

Required / Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
• 4+ years of experience in Physical Design, CAD Methodology, or Design Automation.
• Strong understanding of the complete ASIC/SoC implementation flow from RTL to GDSII Signoff.
• Experience developing automation solutions using Python, Tcl, Perl, Shell, or C++.
• Hands‑on experience with industry‑standard EDA tools and flow customization.
• Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).
• Strong knowledge of hierarchical and top‑down design methodologies.
• Experience in Physical Design flow automation, CAD infrastructure, and methodology development.
• Exposure to AI/ML or LLM‑based solutions for EDA automation and productivity enhancement.
• Excellent problem‑solving, debugging, and cross‑functional collaboration skills.

Tools & Skills

• Synopsys: Design Compiler (DC), Fusion Compiler (FC), IC Compiler II (ICC2), PrimeTime (PT),ICV, StarRC
• Cadence: Innovus, Tempus, Voltus, Pegasus
• Siemens/Mentor: Calibre DRC, LVS, ERC
• Programming: Python, Tcl, Perl, Shell, C++
• Automation: Workflow development, data pipelines, quality dashboards, methodology deployment