SoC Constraints Design Engineer, Silicon

Google LLC; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Google Silicon is seeking a SoC Constraints Design Engineer to drive timing constraints development, validation, and sign-off for complex SoCs powering Pixel and other devices. You will collaborate with RTL, architecture, and EDA teams to deliver robust, area- and power-efficient designs.

You will own timing goals, set up timing analysis flows, and work with implementation engineers to meet deadlines while ensuring cross-domain robustness across clocks and CDC strategies.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; equivalent practical experience.
• 4 years of experience with digital logic design principles and RTL design concepts.
• 1 year of experience with Static Timing Analysis, constraints development and validation, sign-off corner definitions, process margining, and setting timing goals with technology scaling/PDK changes.
• Experience with scripting languages (Python, Perl, Tcl) to automate workflows, parse EDA reports, and develop utilities.

Responsibilities

• Collaborate with Architecture/RTL teams to capture timing intent and drive timing convergence.
• Lead development/validation of SDCs for SoC subsystems and top-level integration used in STA and physical design.
• Understand clocking structures and CDC strategies to ensure robust timing across modes.
• Validate constraints across corners/modes using Fishtail/Timevision.
• Work with design teams for sign-off timing convergence; manage constraints promotion/demotion.

Skills

Digital logic

RTL design

Static Timing Analysis

Constraints development

Python scripting

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Equivalent practical experience

Tools

Synopsys Design Constraints

TimeVision

Primetime

Tempus

Fishtail

Job description

SoC Constraints Design Engineer, Silicon

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts.
• 1 year of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology scaling and Process Design Kit (PDK) changes.
• Experience with scripting languages (e.g., Python, Perl, Tcl) to automate workflows, parse electronic design automation (EDA) reports, and develop custom utilities.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience in developing constraints and validating the same using Timing Constraints Manager (e.g., Synopsys)/TimeVision (e.g., Ausdia).
• Experience with liberty timing models and Static Timing Analysis tools (e.g., TCM/TimeVision, Primetime, Tempus).
• Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.
• Understanding of various external Input/Output (IO) protocols.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google Silicon is developing custom silicon solutions that power the future of Google's direct-to-consumer products, including Pixel and other devices. We combine the best of Google's Artificial Intelligence (AI), Software, and Hardware to create radically helpful experiences.

In this role, you will be part of a team that pushes boundaries, shaping the next generation of hardware experiences by delivering unparalleled power, performance, area efficiency, and integration. You will be part of Google’s Silicon team, developing hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will drive the complete design constraints development, its validation, working on sign-off timing convergence for designs including deciding the initial timing goals, setting up the timing analysis flows and methodology, and working with the implementation engineers to hit the timing goals.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Collaborate with Architecture/Microarchitecture/ Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence.
• Lead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation.
• Understand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes.
• Design constraints validation across multiple corners/modes using Fishtail/Timevision.
• Work closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.