Analog Layout Engineer

Si14 Semiconductor; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Si14 Semiconductor seeks an experienced analog layout engineer to design physical silicon layouts for high-frequency mixed-signal circuits. Responsibilities include floorplanning, device placement, and routing of critical analog blocks while optimizing for noise, mismatch, parasitics, and area.

The role requires hands-on experience with physical verification flows (DRC, LVS, ERC) and signoff methodologies, plus proficiency with industry tools (Cadence Virtuoso, Mentor/Síemens, Synopsys).

Qualifications

• Experience in designing the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs).
• Floorplanning, device placement, routing of critical analog circuits, and optimization for noise, mismatch, parasitics, and area.
• Run and analyze physical verification checks (DRC, LVS, ERC) and signoff flows; debug issues; document layout revisions and methodologies.

Responsibilities

• Perform layout for analog/mixed-signal ICs with emphasis on noise and precision.
• Conduct floorplanning and placement to optimize routing and area.
• Carry out DRC/LVS/ERC checks and collaborate on signoff processes; maintain layout documentation.

Skills

Layout design - analog/mixed-signal

Device placement

Floorplanning

Routing for analog blocks

Physical verification (DRC/LVS/ERC)

Signoff methodologies

Education

Bachelors or Masters in Electronics/Electrical/VLSI

Tools

Cadence Virtuoso

Mentor/Síemens

Synopsys tools

Job description

Role & responsibilities

• Experience in designing the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).
• Day-to-day tasks include floorplanning, device placement, routing of critical analog circuits, and optimization for noise, mismatch, parasitics, and area.
• The engineer will also run and analyze physical verification checks (DRC, LVS, ERC, and related signoff flows), debug issues, and maintain thorough documentation of layout revisions and methodologies.

Preferred candidate profile

• Strong expertise in Layout Design for analog and mixed-signal ICs, including device placement, routing, floorplanning, and layout optimization
• Hands-on experience with Physical Verification flows, including DRC, LVS, ERC, and familiarity with signoff methodologies.
• Proficiency with industry-standard EDA tools for analog layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys tools or similar).
• Knowledge of CMOS process technologies, device physics fundamentals, matching techniques, and layout strategies for low-noise and high-precision circuits.
• Minimum 5+ years of relevant experience in analog layout engineering within the semiconductor or VLSI domain.
• Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or a closely related discipline.