Analog Layout Engineer | 4+ Yrs

leadIC Design Pvt Ltd; Pune District, Bengaluru; Hybrid; INR 900,000 - 1,800,000; Full time

Benefits offered by this job

Competitive compensation

Global client exposure

Job summary

LeadIC Design Pvt Ltd in India seeks Analog Layout Engineers with 4–10 years of experience on TSMC 2nm/3nm/5nm/7nm nodes. Cadence Virtuoso proficiency is required, and openings are in Pune and Bengaluru. You will contribute to the physical design of cutting‑edge chips for global clients, collaborating with design teams across locations. Immediate to 30 days notice period.

Qualifications

• Experience in analog layout for advanced nodes (2nm–7nm).
• Cadence Virtuoso experience is required.
• Location: Pune or Bengaluru, India.

Skills

Analog Layout

TSMC 2nm/3nm/5nm/7nm experience

Tools

Cadence Virtuoso

Job description

Hiring Analog Layout Engineers (4-10 yrs) with TSMC 2nm/3nm/5nm/7nm experience. Cadence Virtuoso required. Locations: Pune & Bengaluru. Notice period: Immediate-30 days.

Perks and benefits

Competitive compensation & global client exposure

Skills highlighted with '' are preferred keyskills

Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability. We have our engineering teams across India, Germany and Canada,

Analog Layout Engineer

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