Analog Layout Engineer

UST; Bengaluru; On-site; INR 1,200,000 - 1,700,000; Full time

Job summary

UST is seeking a highly motivated Analog Layout Engineer to join our semiconductor design team in Bengaluru. The role focuses on physical implementation of high-performance analog and mixed-signal circuits, ensuring compliance with design rules and manufacturability.

You will develop custom analog, mixed-signal, and RF layouts, perform floorplanning and placement, and collaborate with circuit designers, verification engineers, and foundry teams to meet performance, area, and schedule targets.

Qualifications

• Experience in physical design of analog and mixed-signal circuits.
• Ability to implement layouts for high-performance technologies.
• Familiarity with DRC, LVS, and ERC checks and post-layout signoff.

Responsibilities

• Develop and implement custom analog, mixed-signal, and RF layouts for advanced semiconductor technologies.
• Perform layout of critical analog blocks such as Op-Amps, Bandgap References, LDOs, PLLs, ADCs/DACs, Charge Pumps.
• Ensure device matching, symmetry, shielding, and parasitic optimization.

Skills

Analog layout

Mixed-signal layout

RF layout

Floorplanning

Placement

DRC

LVS

ERC

Parasitic extraction

Post-layout signoff

Job description

We are seeking a highly motivated Analog Layout Engineer to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal circuits, ensuring compliance with technology design rules, matching requirements, and manufacturability constraints.

Key Responsibilities:

• Develop and implement custom analog, mixed-signal, and RF layouts for advanced semiconductor technologies.
• Perform layout of critical analog blocks such as:
• Operational Amplifiers (Op-Amps)
• Bandgap References
• LDO Regulators
• PLLs
• ADCs/DACs
• Charge Pumps
• Ensure proper device matching, symmetry, shielding, and parasitic optimization.
• Conduct floorplanning and placement of analog blocks.
• Perform layout verification activities:
• DRC (Design Rule Check)
• LVS (Layout Versus Schematic)
• ERC (Electrical Rule Check)
• Density Checks
• Extract parasitics and support post-layout simulation and signoff activities.
• Collaborate closely with circuit designers, verification engineers, and foundry teams.
• Debug and resolve layout-related issues to meet performance, area, and schedule targets.
• Follow foundry design guidelines and process-specific requirements.