Analog Layout Engineer

Lakshya Software Technologies Pvt. Ltd.; Hyderabad; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Lakshya Software Technologies Pvt. Ltd. in Hyderabad is seeking an Analog Layout Engineer with 3-5 years of experience to contribute to design and full chip level integration support.

You will verify layouts with LVS/DRC, ensure on-time delivery, and collaborate with teams in India, US, and Japan. Proficiency in Cadence VLE/VXL and Calibre LVS/DRC is required; B.Tech/M.Tech.

Qualifications

• 3-5 year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Hands-on experience with critical analog layout of blocks like Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, current mirrors, comparator, differential amplifier, etc.
• Strong understanding of analog layout fundamentals: matching, EM, latch-up, coupling, cross-talk, IR-drop, parasitics.
• Understanding layout effects on speed, capacitance, power and area.
• Ability to interpret design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in physical layout verification.
• Knowledge of basic active/passive devices: R, L, C, MOSFETs.
• Scripting and automation experience is a plus.
• Excellent verbal and written communication skills.

Responsibilities

• Design and development of analog, mixed-signal, and custom digital blocks and full chip integration support.
• Perform layout verification: LVS/DRC/Antenna checks, quality checks and documentation.
• Ensure on-time delivery of block-level layouts with acceptable quality.
• Contribute to effective project-management.
• Communicate with engineering teams in India, US, and Japan to assure project success.

Skills

Analog layout

Cadence VLE/VXL

Calibre DRC/LVS

Layout verification

Education

B.Tech/MTech

Tools

Calibre

Job description

Job Description

Experience : 3 to 5 Years

Location :Hyderabad

Mode Of Interview : In-Person

Role : Analog Layout Engineer

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Contribute to effective project-management.
• Effectively communicating with engineering teams in the India, US, and Japan to assure the success of the layout project.

Qualification/Requirements

• 3-5 year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in Physical layout verification.
• Good understanding of basic active and passive devices such as R,L, C and MOSFETs
• Scripting and automation experience is good to have but not mandatory.
• Excellent verbal and written communication skills.

Qualifications: B.Tech/MTech