Timing & Physical Design Automation Engineer

eTeam; Cork; On-site; EUR 60,000 - 85,000; Full time

Job summary

eTeam in Cork, Ireland seeks a candidate with hands-on timing characterization experience and strong scripting skills to automate flows and improve productivity across libraries and sign-off processes. The role covers correlation between timing tools and Spice simulations, and involves modern P&R/STA practices for ASIC design.

The ideal candidate has experience with library characterization, aging reliability modeling, and tools such as Hspice, PrimeTime, and FusionCompiler, with a willingness

Qualifications

• Hands-on experience in timing related activities such as library, LVF, AOCV/POCV/SOCV.
• Experience with correlation between timing sign-off tools and Spice simulations.
• Strong scripting ability in Python/Perl/TCL/Bash.
• Knowledge of P&R, STA, and aging reliability modeling.
• Willingness to learn new methodologies.

Responsibilities

• Characterization, timing, power and pin-cap lib modeling for Analog and GPIOs (1-3 years).
• Work with tools like Silicon Smart, Hspice, Primesim, AFS, Spectre; Liberty format descriptions.
• Use Python-based scripting to automate flows and improve productivity.
• Support ASIC Physical Design flow including synthesis, floorplanning, placement, CTS, routing, and STA.

Job description

eTeam in Cork, Ireland seeks a candidate with hands-on timing characterization experience and strong scripting skills to automate flows and improve productivity across libraries and sign-off processes. The role covers correlation between timing tools and Spice simulations, and involves modern P&R/STA practices for ASIC design.

The ideal candidate has experience with library characterization, aging reliability modeling, and tools such as Hspice, PrimeTime, and FusionCompiler, with a willingness