STA Design Engineer - ASIC / Low Power

European Tech Recruit; Cork; On-site; EUR 60,000 - 90,000; Full time

Job summary

European Tech Recruit is partnering with a leading semiconductor company to hire an STA Design Engineer for Cork, Ireland. You will conduct complex timing signoff, drive closure for next‑generation ASICs, and collaborate with RTL, Synthesis and Physical Design teams to optimize PPA.

You should have 4+ years in Static Timing Analysis, strong experience with PrimeTime/Tempus, ECO tools, and strong Python/TCL/Perl scripting skills to automate timing data processing.

Qualifications

• 4+ years of experience in Static Timing Analysis.
• Proficient in PrimeTime, PrimeShield or Tempus for hierarchical analysis.
• Experience with ECO tools like Tweaker, PrimeClosure, PTECO, Tempus ECO.
• Strong automation scripting with Python, TCL or Perl.
• Deep understanding of the ASIC design flow RTL-to-GDS.

Responsibilities

• Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs.
• Evaluate block-level and top-level timing on gate-level PNR netlists.
• Provide feedback to RTL, Synthesis, and Physical Design teams to improve PPA.
• Create and execute Timing ECOs to resolve timing violations.
• Enhance STA flow accuracy and reduce turnaround time.
• Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.

Skills

Static Timing Analysis

Automation scripting

ASIC design flow knowledge

Tools

PrimeTime

PrimeShield

Tempus

Tweaker

PrimeClosure

PTECO

Tempus ECO

Job description

We are partnered with a global leader in semiconductors and wireless technology focused on developing high-performance, low-power ASIC solutions for advanced cores and SOCs (System-on-Chips). The team are looking to hire an STA Engineer to take responsibility for conducting complex timing signoff activities and drive closure for next-generation products.

This is a permanent working opportunity based in Cork, Ireland.

Key responsibilities for this STA Design Engineer position:

• Perform Static Timing Analysis (STA) and drive timing closure for complex cores and full-chip SOCs (e.g., in the Snapdragon family).
• Evaluate block-level and top-level timing on gate-level PNR netlists.
• Provide critical feedback to the RTL, Synthesis, and Physical Design teams to improve Power, Performance, and Area (PPA).
• Create and execute Timing Engineering Change Orders (ECOs) to resolve critical timing violations.
• Enhance techniques and methodologies for timing closure and STA flow accuracy to reduce turnaround time (TAT).
• Develop automation scripts (Python, TCL, or Perl) for timing/power data mining and processing.

Key requirements:

• 4+ years of related work experience in Static Timing Analysis.
• Expert proficiency in STA tools such as PrimeTime, PrimeShield, or Tempus for hierarchical analysis in large SoCs.
• Hands-on experience with ECO tools (e.g., Tweaker, PrimeClosure, PTECO, Tempus ECO) for timing closure.
• Highly proficient in automation scripting using Python, TCL, or Perl.
• Strong knowledge of the complete ASIC design flow (RTL-to-GDS).

Keywords:

STA Design Engineer / Static Timing Analysis / STA / Timing Closure / ASIC Design / SOC / PrimeTime / Tempus / Timing ECO / PPA Optimization / Gate-Level Netlist / Python / TCL / Physical Design / RTL / Synthesis / Semiconductor / High-Performance Cores